LPC2387 datasheet(29/52 Pages) NXP

29 / 52 page

LPC2387_3

Product data sheet

Rev. 03 — 29 October 2008

29 of 52

NXP Semiconductors

LPC2387

Single-chip 16-bit/32-bit microcontroller

The PLL input, in the range of 32 kHz to 50 MHz, may initially be divided down by a value

‘N’, which may be in the range of 1 to 256. This input division provides a wide range of

output frequencies from the same input frequency.

Following the PLL input divider is the PLL multiplier. This can multiply the input divider

output through the use of a Current Controlled Oscillator (CCO) by a value ‘M’, in the

range of 1 through 32768. The resulting frequency must be in the range of 275 MHz to

550 MHz. The multiplier works by dividing the CCO output by the value of M, then using a

phase-frequency detector to compare the divided CCO output to the multiplier input. The

error value is used to adjust the CCO frequency.

The PLL is turned off and bypassed following a chip Reset and by entering Power-down

mode. PLL is enabled by software only. The program must conﬁgure and activate the PLL,

wait for the PLL to Lock, then connect to the PLL as a clock source.

7.24.3 Wake-up timer

The LPC2387 begins operation at power-up and when awakened from Power-down mode

by using the 4 MHz IRC oscillator as the clock source. This allows chip operation to

resume quickly. If the main oscillator or the PLL is needed by the application, software will

need to enable these features and wait for them to stabilize before they are used as a

clock source.

When the main oscillator is initially activated, the wake-up timer allows software to ensure

that the main oscillator is fully functional before the processor uses it as a clock source

and starts to execute instructions. This is important at power on, all types of Reset, and

whenever any of the aforementioned functions are turned off for any reason. Since the

oscillator and other functions are turned off during Power-down mode, any wake-up of the

processor from Power-down mode makes use of the wake-up Timer.

The Wake-up Timer monitors the crystal oscillator to check whether it is safe to begin

code execution. When power is applied to the chip, or when some event caused the chip

to exit Power-down mode, some time is required for the oscillator to produce a signal of

sufﬁcient amplitude to drive the clock logic. The amount of time depends on many factors,

including the rate of VDD(3V3) ramp (in the case of power on), the type of crystal and its

electrical characteristics (if a quartz crystal is used), as well as any other external circuitry

(e.g., capacitors), and the characteristics of the oscillator itself under the existing ambient

conditions.

7.24.4 Power control

The LPC2387 supports a variety of power control features. There are four special modes

of processor power reduction: Idle mode, Sleep mode, and Power-down mode. The CPU

clock rate may also be controlled as needed by changing clock sources, reconﬁguring PLL

values, and/or altering the CPU clock divider value. This allows a trade-off of power versus

processing speed based on application requirements. In addition, Peripheral Power

Control allows shutting down the clocks to individual on-chip peripherals, allowing ﬁne

tuning of power consumption by eliminating all dynamic power use in any peripherals that

are not required for the application. Each of the peripherals has its own clock divider which

provides even better power control.

The LPC2387 also implements a separate power domain in order to allow turning off

power to the bulk of the device while maintaining operation of the RTC and a small SRAM,

referred to as the battery RAM.

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