TDA8950_1

© NXP B.V. 2008. All rights reserved.

Preliminary data sheet

Rev. 01 — 9 September 2008

17 of 39

NXP Semiconductors

TDA8950

2

× 150 W class-D power amplifier

13. Application information

13.1 Mono BTL application

When using the power amplifier in a mono BTL application the inputs of both channels

must be connected in parallel and the phase of one of the inputs must be inverted (see

Figure 7). In principle the loudspeaker can be connected between the outputs of the two

single-ended demodulation filters.

13.2 Pin MODE

For pop noise-free start-up, an RC time-constant must be applied on pin MODE. The

bias-current setting of the VI-converter input is directly related to the voltage on pin

MODE. In turn the bias-current setting of the VI converters is directly related to the DC

output offset voltage. Thus a slow dV/dt on pin MODE results in a slow dV/dt for the

DC output offset voltage, resulting in pop noise-free start-up. A time-constant of 500 ms is

sufficient to guarantee pop noise-free start-up (see also Figure 4, 5 and 8).

13.3 Output power estimation

13.3.1 SE

Maximum output power:

(1)

Maximum current internally limited to 9.2 A:

(2)

Variables:

through the load and the ripple current. The value of the ripple current is dependent on the

coil inductance and voltage drop over the coil.

P

o 0.5%

()

R

L

R

L

R

DSon hs

()

R

sL

++

-----------------------------------------------------

V

P

1t

min

0.5

×

f

osc

–

()

×

×

2

2R

L

----------------------------------------------------------------------------------------------------------------------------------

=

I

opeak

()

V

P

1t

min

0.5 f

osc

×

–

()

×

R

L

R

DSon hs

()

R

sL

++

--------------------------------------------------------------

=