F71806 datasheet(16/109 Pages) FINTEK

16 / 109 page

July, 2007

V0.26P

F71806

6 Function Description

6.1 Power on Strapping Options

The F71806 provides four pins for power on hardware strapping to select functions. There is a form to describe how to

set the functions you want.

Pin No.

Symbol

Value

Description

Pin31/33/34/48/84 will be defined a Open Drain pin. (Default)

RST_DRV

Pin31/33/34/48/84 will be defined a Drive pin.

Fan control mode: PWM mode. ( Default)

PWM_DC

Fan control mode: Linear mode.

Chip selection in configuration 4E. (Default)

124

Config4E_2E

Chip selection in configuration 2E.

6.2 ACPI

The Advanced Configuration and Power Interface (ACPI) is a system for controlling the use of power in a

computer. It lets computer manufacturer and user to determine the computer’s power usage dynamically.

There are three ACPI states that are of primary concern to the system designer and they are designated S0,

S3 and S5. S0 is a full-power state; the computer is being actively used in this state. The other two are called

sleep states and reflect different power consumption when power-down. S3 is a state that the processor is

powered down but the last procedural state is being stored in memory which is still active. S5 is a state that

memory is off and the last procedural state of the processor has been stored to the hard disk. Take S3 and S5

as comparison, since memory is fast, the computer can quickly come back to full-power state, the disk is slower

than the memory and the computer takes longer time to come back to full-power state. However, since the

memory is off, S5 draws the minimal power comparing to S0 and S3.

It is anticipated that only the following state transitions may happen:

S0→S3, S0→S5, S5→S0, S3→S0 and S3→S5.

Among them, S3→S5 is illegal transition and won’t be allowed by state machine. It is necessary to enter S0 first

in order to get to S5 from S3. As for transition S5→S3 will occur only as an immediate state during state

transition from S5→S0. It isn’t allowed in the normal state transition.

The below diagram described the timing, the always on and always off, keep last state could be set in

control register. In keep last state mode, one register will keep the status of before power loss. If it is power on

F71806 Datasheet(PDF) 16 Page - Feature Integration Technology Inc.