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F71806 Datasheet(PDF) 39 Page - Feature Integration Technology Inc.

Part # F71806
Description  Super H/W Monitor LPC IO
PDF  109 Pages
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Manufacturer  FINTEK [Feature Integration Technology Inc.]
Direct Link  http://www.fintek.com.tw/eng
Logo FINTEK - Feature Integration Technology Inc.

F71806 Datasheet(HTML) 39 Page - Feature Integration Technology Inc.

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July, 2007
V0.26P
37
F71806
7.2.3.6
Tape Drive Register
 Base + 3
Bit
Name
R/W Default
Description
7-6 Reserved
R
00
Reserved. Return 00b when read.
5-4 TYPEID
R
11
Reserved in normal function, return 11b when read.
If 3 mode FDD function is enabled. These bits indicate the drive type ID.
3-2 Reserved
R
11
Reserved. Return 11b when read in normal function.
Return 00b when read in 3 mode FDD function.
1-0 TAPESEL
R/W
0
These bits assign a logical drive number to be a tape drive.
7.2.3.7
Main Status Register
 Base + 4
Bit
Name
R/W Default
Description
7
RQM
R
0
Request for Master indicates that the controller is ready to send or receive data
from the uP through the FIFO.
6
DIO
R
0
Data I/O (direction):
0: the controller is expecting a byte to be written to the Data Register.
1: the controller is expecting a byte to be read from the Data Register.
5
NON_DMA
R
0
Non DMA Mode:
0: the controller is in DAM mode.
1: the controller is interrupt or software polling mode.
4
FDC_BUSY
R
0
This bit indicate that a read or write command is in process.
3
DRV3_BUSY
R
0
FDD number 3 is in seek or calibration condition. FDD number 3 is not support
in this design.
2
DRV2_BUSY
R
0
FDD number 2 is in seek or calibration condition. FDD number 2 is not support
in this design.
1
DRV1_BUSY
R
0
FDD number 1 is in seek or calibration condition. FDD number 1 is not support
in this design.
0
DRV0_BUSY
R
0
FDD number 0 is in seek or calibration condition.
7.2.3.8
Data Rate Select Register
 Base + 4
Bit
Name
R/W Default
Description
7
SOFTRST
W
0
A 1 written to this bit will software reset the controller. Auto clear after reset.
6
PWRDOWN
W
0
A 1 to this bit will put the controller into low power mode which will turn off the
oscillator and data separator circuits.
5
Reserved
-
-
Return 0 when read.



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