12-124

HV623

Option 1

Option 2

V

BIAS

V

CTL

R

CTL

I

PP

V

BIAS

V

CTL

R

CTL

I

PP

(V)

(V)

(

Ω)

(mA)

(V)

(V)

(

Ω)

(mA)

0

0.1

56K

2

-1.0

0

56K

4

0

1.0

56K

7

-2.0

0

56K

5.5

Symbol

Parameter

Min

Typ

Max

Units

Conditions

f

SC

Shift clock operating frequency

10.2

MHz

f

DIN

Data-in frequency

20.4

MHz

t

SS

CSI/CSO pulse to shift clock setup time

40

ns

t

HS

CSI/CSO pulse to shift clock hold time

0

ns

t

WA

CSI pulse width

49

ns

t

DS

Data to shift clock setup time

20

ns

t

DH

Data to shift clock hold time

0

ns

t

WD

Data-in pulse width

24

ns

t

WLC

Load count pulse width

98

ns

t

DLCR

Load count to ramp delay

1

µs

t

DRCC

1

Ramp to count clock delay

0.47

µs

t

DSL

Shift clock to load count delay time

98

ns

t

CSC

Shift clock cycle time

98

ns

t

WSC

Shift clock pulse width

49

ns

t

CCC

Count clock cycle time

98

ns

t

WCC

Count clock pulse width

49

ns

Note 1: Count clock starts counting after 0.47

µs min. This is equivalent to a time duration for a linear ramp V

ramp size time of 12

µs for V

Logic Timing

Electrical Characteristics

V

Note 2: The maximum ramp hold time may be longer than 15

µs, but the output voltage HV

Table 1:

Schemes to control I

Symbol

Parameter

Min

Typ

Max

Units

Conditions

Cycle time of ramp signal

15

µs

Ramp rise time

12

µs

2

Ramp hold time

2

15

µs

Ramp fall time

TBD

3

µs

HV623

VCTL

VCTL

RCTL

RCTL

VBIAS

-

+

-

+