12-125

Pin #

Name

Function

30-36

D1-D7

Inputs for binary-format parallel data.

26

SC (Shift Clock)

Triggers data on both rising and falling edges. This implies that the data rate is always twice the clock

rate (data rate = 20MHz max if clock rate = 10MHz max).

22

CSI (Chip

Input pin for the chip select pulse (when DIR is high).

Select Input)

Output pin for the chip select pulse (when DIR is low).

43

CSO (Chip

Input pin for the chip select pulse (when DIR is low).

Select Output)

Output pin for the chip select pulse (when DIR is high).

40

LC

Input for a pulse whose rising edge causes data from the input latches to enter the comparator latches,

(Load Count)

and whose falling edge initiates the conversion of this binary data to an output level (D-to-A).

Also, the HV

42

CC (Count Clock) Input to the count clock generator whose increments are compared to the data in the comparator latches.

18, 47

V

R

High-voltage ramp input for charging the output stage hold capacitors (C

This input can be linear or non-linear as desired.

28

DIR

When this pin is connected to V

27, 38

LVGND

This is ground for the logic section.

HVGND and LVGND should be connected together externally.

17, 48

HVGND

This is ground for the high-voltage (output) section.

HVGND and LVGND should be connected together externally.

19, 45

V

PP

This input biases the output source followers.

1-16

HV

High-voltage outputs.

49-64

21

Low-voltage analog supply voltage.

29

Low-voltage digital supply voltage.

24

particular panel). The combination of V

±0.2V of delta voltage between high voltage outputs of the same level at all gray levels.

25

R

CTL

Current sense resistor to ground to prevent output voltage from being affected by its adjacent outputs

(R

Pin Definitions

Input and Output Equivalent Circuits

Input

GND

(Logic)

Logic Inputs

GND

(Logic)

Data Out

Logic Data Output

HV623