12-126

Functional Block Diagram

Output

Stage

Latches and

Comparators

Latches and

Comparators

Latches and

Comparators

Latches and

Comparators

Load

Count

CC

Clear

Dual

16-bit

Shift Registers

GND

Output

Stage

Data In

Buffers

Output

Stage

Counter

Reset

Counter

Data

Latches

Data

Latches

Data

Latches

Data

Latches

RS

F/F

RS

F/F

RS

F/F

RS

F/F

7

7

7

7

7

7

7

7

7

L/E

L/E

L/E

L/E

Clear

Pulse

Generator

Load

Count

Buffer

Count

Clock

Buffer

SC

SC

SC

Shift

Clock

Buffer

CSI

I/O

Buffers

CC

LC

D1

D7

DIR

CSO

I/O

Buffers

See Output Stage Detail

Output

Stage

1

2

31

32

SC = Shift Clock

LC = Load Count

CC = Count Clock

CSI = Chip Select Input

CSO = Chip Select Output

*Strobe = twice the SC frequency

Logic

70V

HV623

0V

Output

Stage

HVGND

LVGND

+

–

1K

Ω V

tst

10K

Ω

+

-

1. Set HV

2. Apply V

3. Apply a step voltage of 70V at V

4. Measure voltage across the 1K

Ω resistor.

5. Output source current can be calculated by using

V

tst

.

1K

Internal

Logic

&

Bias

Circuit

Test Circuit

High-voltage Analog Output Source Current (I

For gray shade #1 (000 0000)

Output Stage Detail

HV623