LTC2365 datasheet(21/24 Pages) LINER

21 / 24 page

LTC2365/LTC2366

23656f

Figure 20. Power Supply Ground Practice

High quality tantalum and ceramic bypass capacitors

should be used at the VDD and VREF pins as shown in the

Typical Application circuit on the ﬁrst page of this data

sheet. For optimum performance, a 10μF surface mount

AVX capacitor with a 0.1μF ceramic is recommended for

the VDD pin and a 4.7μF surface mount AVX capacitor

with a 0.1μF ceramic is recommended for the VREF and

OVDD pins. Alternatively, 4.7μF and 10μF ceramic chip

capacitors such as Murata GRM235Y5V106Z016 may

be used. The capacitors must be located as close to the

pins as possible. The traces connecting the pins and the

bypass capacitors must be kept short and should be made

as wide as possible.

APPLICATIONS INFORMATION

Figure 20 shows the recommended system ground con-

nections. All analog circuitry grounds should be terminated

at the LTC2365/LTC2366. The ground return from the

LTC2365/LTC2366 to the power supply should be low

impedancefornoisefreeoperation.Digitalcircuitrygrounds

must be connected to the digital supply common.

In applications where the ADC data outputs and control sig-

nals are connected to a continuously active microprocessor

bus, it is possible to get errors in the conversion results.

These errors are due to feedthrough from the micropro-

cessor to the successive approximation comparator. The

problem can be eliminated by forcing the microprocessor

into a Wait state during conversion or by using three-state

buffers to isolate the ADC data bus.

23656 F20

GND

AIN

VDD

CAIN

SDO

SCK

CVDD

PIN 1

VIAS TO GROUND PLANE

10μF

LTC2365 Datasheet(PDF) 21 Page - Linear Technology

LTC2365 Datasheet(HTML) 21 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Datasheet Download

Link URL