LTC2365 datasheet(5/24 Pages) LINER

5 / 24 page

LTC2365/LTC2366

23656f

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: All voltage values are with respect to GND.

Note 3: When this pin, AIN, is taken below GND or above VDD, it will be

clamped by internal diodes. These products can handle input currents

greater than 100mA below GND or above VDD without latchup.

Note 4: VDD = OVDD = VREF = 2.35V to 3.6V, fSMPL = fSMPL(MAX) and fSCK =

fSCK(MAX) unless otherwise speciﬁed.

Note 5: Integral linearity is deﬁned as the deviation of a code from a

straight line passing through the actual endpoints of the transfer curve. The

deviation is measured from the center of the quantization band.

Note 6: Linearity, offset and gain speciﬁcations apply for a single-ended

AIN input with respect to GND.

Note 7: Typical RMS noise at code transitions.

Note 8: Guaranteed by characterization. All input signals are speciﬁed with

tr = tf = 2ns (10% to 90% of VDD) and timed from a voltage level of 1.6V.

Note 9: All timing speciﬁcations given are with a 10pF capacitance load.

With a capacitance load greater than this value, a digital buffer or latch

must be used.

Note 10: Minimum fSCK at which speciﬁcations are guaranteed.

Note 11: The time required for the output to cross the VIH or VIL voltage.

Note 12: Guaranteed by design, not subject to test.

Note 13: High temperatures degrade operating lifetimes. Operating lifetime

is derated at temperatures greater than 105°C.

SYMBOL

PARAMETER

CONDITIONS

LTC2365

LTC2366

UNITS

MIN

TYP

MAX

MIN

TYP

MAX

fSMPL(MAX)

Maximum Sampling Frequency

(Notes 8, 9)

MHz

fSCK

Shift Clock Frequency

(Notes 8, 9, 10)

0.5

MHz

tSCK

Shift Clock Period

62.5

2000

20.8

2000

tTHROUGHPUT Minimum Throughput Time, tACQ + tCONV

1000

333

tACQ

Acquisition Time

l 181.5

tCONV

Conversion Time

l 818.5

277

tQUIET

SDO Hi-Z State to CS ↓

(Notes 8, 9)

Minimum Positive or Negative CS Pulse Width (Notes 8)

SCK↓ Setup Time After CS ↓

(Notes 8)

2000

SDO Enabled Time After CS ↓

(Notes 9, 11, 12)

SDO Data Valid Access Time After SCK↓

(Notes 8, 9, 11)

SCK Low Time

40%

tSCK

SCK High Time

40%

tSCK

SDO Data Valid Hold Time After SCK↓

(Notes 8, 9, 11)

SDO Into Hi-Z State Time After SCK↓

(Notes 9, 12)

SDO Into Hi-Z State Time After CS ↑

(Notes 9, 12)

4.2

tPOWER-UP

Power-up Time from Sleep Mode

See Sleep Mode section

1000

333

TIMING CHARACTERISTICS The l denotes the speciﬁcations which apply over the full operating temperature

range, otherwise speciﬁcations are at TA = 25°C. (Note 4)

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