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LTC4085

4085fc

The nearest 1% value for RNOM is 115K. This is the value

used to bias the NTC thermistor to get cold and hot trip

points of approximately 0°C and 44°C respectively. To ex-

tend the delta between the cold and hot trip points a resistor

(R1) can be added in series with RNTC. (see Figure 3b).

The values of the resistors are calculated as follows:

NOM

COLD

HOT

–

.– .

.–

2 815 0 4086

0 4086

2 815 0..

•–

–

4086

⎛

⎝⎜

⎞

⎠⎟ ()

COLD

HOT

where RNOM is the value of the bias resistor, RHOT and

RCOLD are the values of RNTC at the desired temperature

trip points. Continuing the example from before with a

desired hot trip point of 50°C:

NOM

COLD

HOT

–

.– .

•.

– .

2 815 0 4086

100

3 266 0 360

2 815 0 4086

120 8 121

110

()

.– .

k nearest

0 4086

2 815 0 4086

3 266 0 3602

k•

.– .

•.

– .

⎛

⎝⎜

⎞

⎠⎟ ()

–

–.

0 3602

13 3 13 3

⎡

⎣

⎢

⎤

⎦

⎥

k is nearest

The ﬁnal solution is as shown in Figure 3b where

RNOM = 121k, R1 = 13.3k and RNTC = 100k at 25°C

Using the WALL Pin to Detect the Presence of a Wall

Adapter

The WALL input pin identiﬁes the presence of a wall

adapter (the pin should be tied directly to the adapter

output voltage). This information is used to disconnect the

input pin, IN, from the OUT pin in order to prevent back

conduction to whatever may be connected to the input.

It also forces the ACPR pin low when the voltage at the

WALL pin exceeds the input threshold. In order for the

presence of a wall adapter to be acknowledged, both of

the following conditions must be satisﬁed:

1. The WALL pin voltage exceeds VWAR (approximately

4.25V); and

2. The WALL pin voltage exceeds VWDR (approximately

75mV above VBAT)

The input power path (between IN and OUT) is re-enabled

and the ACPR pin assumes a high impedance state when

either of the following conditions is met:

1. The WALL pin voltage falls below VWDF (approximately

25mV above VBAT); or

2. The WALL pin voltage falls below VWAF (approximately

3.12V)

Each of these thresholds is suitably ﬁltered in time to

prevent transient glitches on the WALL pin from falsely

triggering an event.

Power Dissipation

The conditions that cause the LTC4085 to reduce charge

current due to the thermal protection feedback can be

approximated by considering the power dissipated in the

part. For high charge currents and a wall adapter applied to

VOUT, the LTC4085 power dissipation is approximately:

PD = (VOUT – VBAT) • IBAT

Where, PD is the power dissipated, VOUT is the supply

voltage, VBAT is the battery voltage, and IBAT is the battery

charge current. It is not necessary to perform any worst-

case power dissipation scenarios because the LTC4085

will automatically reduce the charge current to maintain

the die temperature at approximately 105°C. However, the

approximate ambient temperature at which the thermal

feedback begins to protect the IC is:

TA = 105°C – PD • θJA

TA = 105°C – (VOUT – VBAT) • IBAT • θJA

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