PCI1225 datasheet(2/131 Pages) TI

2 / 131 page

PCI1225 GHK/PDV

PC CARD CONTROLLERS

SCPS035B – MAY 1998 – REVISED – MAY 2000

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

description

The TI PCI1225 is a high-performance PCI-to-PC Card controller that supports two independent card sockets

compliant with the 1997 PC Card Standard. The PCI1225 provides a rich feature set that makes it the best

choice for bridging between PCI and PC Cards in both notebook and desktop computers. The 1997 PC Card

Standard retains the 16-bit PC Card specification defined in PCMCIA Release 2.2 and defines the new 32-bit

PC Card (CardBus), capable of full 32-bit data transfers at 33 MHz. The PCI1225 supports any combination

of 16-bit and CardBus PC Cards in the two sockets, powered at 5 V or 3.3 V, as required.

The PCI1225 is compliant with the PCI Local Bus Specification 2.2, and its PCI interface can act as either a PCI

master device or a PCI slave device. The PCI bus mastering is initiated during 16-bit PC Card DMA transfers

or CardBus PC Card bridging transactions. The PCI1225 is also compliant with the latest

PCI Bus Power

Management Interface Specification.

All card signals are internally buffered to allow hot insertion and removal without external buffering. The PCI1225

is register compatible with the Intel 82365SL-DF ExCA controller. The PCI1225 internal data path logic allows

the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for maximum performance. Independent

buffering and a pipeline architacture provide an unsurpassed performance level with sustained bursting. The

PCI1225 can also be programmed to accept fast posted writes to improve system-bus utilization.

Multiple system-interrupt signaling options are provided, including: parallel PCI, parallel ISA, serialized ISA, and

serialized PCI. Furthermore, general-purpose inputs and outputs are provided for the board designer to

implement sideband functions. Many other features designed into the PCI1225, such as socket activity

light-emitting diode (LED) outputs, are discussed in detail throughout the design specification.

An advanced complementary metal-oxide semiconductor (CMOS) process is used to achieve low

system-power consumption while operating at PCI clock rates up to 33 MHz. Several low-power modes enable

the host power management system to further reduce power consumption.

Unused PCI1225 inputs must be pulled up using a 43-k

W resistor.

PCI1225 Datasheet(PDF) 2 Page - Texas Instruments