PCI1225 datasheet(29/131 Pages) TI

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PCI1225 GHK/PDV

PC CARD CONTROLLERS

SCPS035B – MAY 1998 – REVISED – MAY 2000

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

16-bit PC Card distributed DMA support (continued)

Table 7. Distributed DMA Registers

TYPE

DMA

BASE ADDRESS

OFFSET

Reserved

Page

Current address

00h

Reserved

Page

Base address

Reserved

Current count

04h

Reserved

Base count

N/A

Reserved

N/A

Status

08h

Mode

Reserved

Request

Command

Multichannel

Reserved

N/A

Reserved

0Ch

Mask

Reserved

Master clear

Reserved

The DDMA registers contain control and status information consistent with the 8237 DMA controller; however,

the register locations are reordered and expanded in some cases. While the DDMA register definitions are

identical to those in the 8237 DMA controller of the same name, some register bits defined in the 8237 DMA

controller do not apply to distributed DMA in a PCI environment. In such cases, the PCI1225 implements these

obsolete register bits as read-only, nonfunctional bits. The reserved registers shown in Table 7 are implemented

as read-only and return zeros when read. Write transactions to reserved registers have no effect.

The DDMA transfer is prefaced by several configuration steps that are specific to the PC Card and must be

completed after the PC Card is inserted and interrogated. These steps include setting the proper DREQ signal

assignment, setting the data transfer width, and mapping and enabling the DDMA register set. As discussed

above, this is done through socket DMA register 0 and socket DMA register 1. The DMA register set is then

programmed similarly to an 8237 controller, and the PCI1225 awaits a DREQ assertion from the PC Card

requesting a DMA transfer.

DMA writes transfer data from the PC Card to PCI memory addresses. The PCI1225 accepts data 8 or 16 bits

at a time, depending on the programmed data width, and then requests access to the PCI bus by asserting its

REQ signal. Once the PCI bus is granted in an idle state, the PCI1225 initiates a PCI memory write command

to the current memory address and transfers the data in a single data phase. After terminating the PCI cycle,

the PCI1225 accepts the next byte(s) from the PC Card until the transfer count expires.

DMA reads transfer data from PCI memory addresses to the PC Card application. Upon the assertion of DREQ,

the PCI1225 asserts REQ to acquire the PCI bus. Once the bus is granted in an idle state, the PCI1225 initiates

a PCI memory read operation to the current memory address and accepts 8 or 16 bits of data, depending on

the programmed data width. After terminating the PCI cycle, the data is passed onto the PC Card. After

terminating the PC Card cycle, the PCI1225 requests access to the PCI bus again until the transfer count has

expired.

The PCI1225 target interface acts normally during this procedure and accepts I/O reads and writes to the DDMA

registers. While a DDMA transfer is in progress and the host resets the DMA channel, the PCI1225 asserts TC

and ends the PC Card cycle(s). TC is indicated in the DDMA status register. At the PC Card interface, the

PCI1225 supports demand mode transfers. The PCI1225 asserts DACK during the transfer unless DREQ is

deasserted before TC. TC is mapped to the OE PC Card terminal for DMA write operations and is mapped to

WE PC Card terminal for DMA read operations. The DACK signal is mapped to the PC Card REG signal in all

transfers, and the DREQ terminal is routed to one of three options which is programmed through socket DMA

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