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EP1C20F Datasheet(PDF) 89 Page - Altera Corporation

Part # EP1C20F
Description  Cyclone FPGA Family
PDF  106 Pages
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Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

EP1C20F Datasheet(HTML) 89 Page - Altera Corporation

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Altera Corporation
4–19
May 2008
Preliminary
Timing Model
Tables 4–34 through 4–35 show the external timing parameters on column
and row pins for EP1C6 devices.
Tables 4–36 through 4–37 show the external timing parameters on column
and row pins for EP1C12 devices.
Table 4–34. EP1C6 Column Pin Global Clock External I/O Timing Parameters
Symbol
-6 Speed Grade
-7 Speed Grade
-8 Speed Grade
Unit
Min
Max
Min
Max
Min
Max
tINSU
2.691
—
3.094
—
3.496
—
ns
tINH
0.000
—
0.000
—
0.000
—
ns
tOUTCO
2.000
3.917
2.000
4.503
2.000
5.093
ns
tINSUPLL
1.513
—
1.739
—
1.964
—
ns
tINHPLL
0.000
—
0.000
—
0.000
—
ns
tOUTCOPL L
0.500
2.038
0.500
2.343
0.500
2.651
ns
Table 4–35. EP1C6 Row Pin Global Clock External I/O Timing Parameters
Symbol
-6 Speed Grade
-7 Speed Grade
-8 Speed Grade
Unit
Min
Max
Min
Max
Min
Max
tINSU
2.774
—
3.190
—
3.605
—
ns
tINH
0.000
—
0.000
—
0.000
—
ns
tOUTCO
2.000
3.817
2.000
4.388
2.000
4.963
ns
tINSUPLL
1.596
—
1.835
—
2.073
—
ns
tINHPLL
0.000
—
0.000
—
0.000
—
ns
tOUTCOPL L
0.500
1.938
0.500
2.228
0.500
2.521
ns
Table 4–36. EP1C12 Column Pin Global Clock External I/O Timing
Parameters (Part 1 of 2)
Symbol
-6 Speed Grade
-7 Speed Grade
-8 Speed Grade
Unit
Min
Max
Min
Max
Min
Max
tINSU
2.510
—
2.885
—
3.259
—
ns
tINH
0.000
—
0.000
—
0.000
—
ns
tOUT CO
2.000
3.798
2.000
4.367
2.000
4.940
ns
tINSUPLL
1.588
—
1.824
—
2.061
—
ns



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