EP1C20F datasheet(40/106 Pages) ALTERA

40 / 106 page

2–34

Altera Corporation

Preliminary

May 2008

Cyclone Device Handbook, Volume 1

Figure 2–26 shows the PLL global clock connections.

Figure 2–26. Cyclone PLL Global Clock Connections

Notes to Figure 2–26:

(1)

PLL 1 supports one single-ended or LVDS input via pins

CLK0 and CLK1.

(2)

PLL2 supports one single-ended or LVDS input via pins

CLK2 and CLK3.

(3)

PLL1_OUT and PLL2_OUT support single-ended or LVDS output. If external output is not required, these pins are

available as regular user I/O pins.

(4)

The EP1C3 device in the 100-pin TQFP package does not support external clock output. The EP1C6 device in the

144-pin TQFP package does not support external clock output from PLL2.

Table 2–7 shows the global clock network sources available in Cyclone

devices.

CLK0

CLK1 (1)

PLL1

PLL2

PLL1_OUT (3), (4)

CLK2

CLK3 (2)

PLL2_OUT (3), (4)

Table 2–7. Global Clock Network Sources (Part 1 of 2)

Source

GCLK0

GCLK1

GCLK2

GCLK3

GCLK4

GCLK5

GCLK6

GCLK7

PLL Counter

Output

PLL1 G0

—

—————

PLL1 G1

——

————

PLL2 G0 (1)

—————

—

PLL2 G1 (1)

————

——

Dedicated

Clock Input

Pins

CLK0

—

—————

CLK1 (2)

—

————

CLK2

————

—

CLK3 (2)

—————

—

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