EP1C20F datasheet(36/106 Pages) ALTERA

36 / 106 page

2–30

Altera Corporation

Preliminary

May 2008

Cyclone Device Handbook, Volume 1

The eight global clock lines in the global clock network drive throughout

the entire device. The global clock network can provide clocks for all

resources within the device—IOEs, LEs, and memory blocks. The global

clock lines can also be used for control signals, such as clock enables and

synchronous or asynchronous clears fed from the external pin, or DQS

signals for DDR SDRAM or FCRAM interfaces. Internal logic can also

drive the global clock network for internally generated global clocks and

asynchronous clears, clock enables, or other control signals with large

fanout. Figure 2–22 shows the various sources that drive the global clock

network.

Figure 2–22. Global Clock Generation

Note (1)

Notes to Figure 2–22:

(1)

The EP1C3 device in the 100-pin TQFP package has five

DPCLK pins (DPCLK2, DPCLK3, DPCLK4, DPCLK6, and

DPCLK7).

(2)

EP1C3 devices only contain one PLL (PLL 1).

(3)

The EP1C3 device in the 100-pin TQFP package does not have dedicated clock pins

CLK1 and CLK3.

Global Clock

Network

PLL1

PLL2

(2)

CLK0

CLK1 (3)

CLK2

CLK3 (3)

DPCLK1

DPCLK0

DPCLK4

DPCLK5

DPCLK2

DPCLK3

DPCLK7

DPCLK6

From logic

array

From logic

array

Cyclone Device

EP1C20F Datasheet(PDF) 36 Page - Altera Corporation

EP1C20F Datasheet(HTML) 36 Page - Altera Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL