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EP1C20F Datasheet(PDF) 33 Page - Altera Corporation |
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EP1C20F Datasheet(HTML) 33 Page - Altera Corporation |
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33 / 106 page ![]() Altera Corporation 2–27 May 2008 Preliminary Embedded Memory Figure 2–19. Input/Output Clock Mode in Simple Dual-Port Mode Notes (1), (2) Notes to Figure 2–19: (1) All registers shown except the rden register have asynchronous clear ports. (2) Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both read and write operations. 6 D ENA Q D ENA Q D ENA Q D ENA Q D ENA Q data[ ] D ENA Q wraddress[ ] address[ ] Memory Block 256 ´ 16 512 ´ 8 1,024 ´ 4 2,048 ´ 2 4,096 ´ 1 Data In Read Address Write Address Write Enable Read Enable Data Out outclken inclken inclock outclock wren rden 6 LAB Row Clocks To MultiTrack Interconnect D ENA Q byteena[ ] Byte Enable Write Pulse Generator |
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