HC220 datasheet(7/228 Pages) ALTERA

7 / 228 page

Altera Corporation

1–5

September 2008

Preliminary

Document Revision History

HardCopy II devices are available in the packages shown in Table 1–3.

Document

Revision History

Table 1–4 shows the revision history for this chapter.

Table 1–3. HardCopy II Package Options and I/O Pin Counts

Notes (1), (2)

Package

484-Pin

FineLine BGA

(3)

484-Pin

FineLine BGA

(3)

672-Pin

FineLine BGA

780-Pin

FineLine BGA

1,020-Pin

FineLine BGA

1,508-Pin

FineLine BGA

Type

Wire bond

Flip-chip

Dimension

Pitch (mm)

1.00

Area (mm2)

529

729

841

1,089

1,600

Length × width

(mm × mm)

23 × 23

27 × 27

29 × 29

33 × 33

40 × 40

Device

Maximum User I/O Pins

HC210W

308

HC210

334

HC220

492

494

HC230

698

HC240

742

951

Notes to Table 1–3:

(1)

The Quartus II I/O pin counts include an additional pin (

PLLENA) which is not available as a general-purpose I/O

pin. The

PLLENA pin can only be used to enable the PLLs.

(2)

The I/O pin counts include the dedicated

CLK input pins, which can be used for clock signals or data inputs.

(3)

The EP2S90 FPGA prototype uses a 484-pin hybrid FineLine BGA package. For more information, refer to the

Stratix II Device Handbook.

Table 1–4. Document Revision History (Part 1 of 2)

Date and Document

Version

Changes Made

Summary of Changes

September 2008,

v2.6

Updated chapter number and metadata.

—

June 2007, v2.5

Minor text edits.

—

HC220 Datasheet(PDF) 7 Page - Altera Corporation

HC220 Datasheet(HTML) 7 Page - Altera Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL