THS1060

10-BIT 60 MSPS IF SAMPLING COMMUNICATIONS

ANALOG-TO-DIGITAL CONVERTER

SLAS212 – MARCH 2000

3

POST OFFICE BOX 655303

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

AVDD

2, 5, 12

43, 45, 47

I

Analog power supply

AVSS

1, 11, 13,

41, 42, 44,

46

I

Analog ground return for internal analog circuitry

CLK+

15

I

Clock input

CLK–

16

I

Complementary clock input

D9–D0

25–34

O

Digital data output bits; LSB= D0, MSB = D9 (2s complement output format)

DRVDD

24, 37, 38

I

Digital output driver supply

DRVSS

23, 39, 40

I

Digital output driver ground return

DVDD

17, 20, 22

I

Positive digital supply

DVSS

18, 19, 21

I

Digital ground return

VBG

10

O

Band gap reference. Bypass to ground with a 1

µF and a 0.01 µF chip capacitor.

VCM

48

O

Common mode voltage output. Bypass to ground with a 0.1

µF and a 0.01 µF chip device capacitor.

VIN+

3

I

Analog signal input

VIN–

4

I

Complementary analog signal input

VREFIN –

7

I

External reference input low

VREFIN+

8

I

External reference input high

VREFOUT+

9

O

Internal reference output. Compensate with a 1

µF and a 0.01 µF chip capacitor.

VREFOUT –

6

O

Internal reference output. Compensate with a 1

µF and a 0.01 µF chip capacitor.

detailed description

The THS1060 uses a differential pipeline architecture and assures no missing codes over the full operating

temperature range. The device uses a 1 bit per stage architecture in order to achieve the highest possible

bandwidth. The differential analog inputs are terminated with a 900

Ω resistor. The inputs are then fed to a unity

gain buffer followed by the S/H (sample and hold) stage. This S/H stage is a switched capacitor op-amp based

circuit, see Figure 3. The pipeline is a typical 1 bit per stage pipeline as shown in the functional block diagram.

The digital output of the 10 stages and the last 1 bit flash are sent to a digital correction logic block which then

outputs the final 10 bits.