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TMS320VC5410 Datasheet(PDF) 71 Page - Texas Instruments |
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TMS320VC5410 Datasheet(HTML) 71 Page - Texas Instruments |
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71 / 79 page  TMS320VC5410 FIXEDPOINT DIGITAL SIGNAL PROCESSOR SPRS075D – OCTOBER 1998 – REVISED MAY 2000 71 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 multichannel buffered serial port timing (continued) timing requirements for McBSP as SPI master or slave: [H=0.5tc(CO)] CLKSTP = 11b, CLKXP = 1† (see Figure 39) ’5410-100 ’5410-120 MASTER SLAVE MASTER SLAVE UNIT MIN MAX MIN MAX MIN MAX MIN MAX U tsu(BDRV-BCKXL) Setup time, BDR valid before BCLKX low 12 7 – 6H 12 7 – 6H ns th(BCKXL-BDRV) Hold time, BDR valid after BCLKX low 0 5 + 6H 0 5 + 6H ns † For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. switching characteristics for McBSP as SPI master or slave: [H=0.5tc(CO)] CLKSTP = 11b, CLKXP = 1†‡ (see Figure 39) ’5410-100 ’5410-120 PARAMETER MASTER‡ SLAVE MASTER‡ SLAVE UNIT MIN MAX MIN MAX MIN MAX MIN MAX U th(BCKXH-BFXL) Hold time, BFSX low after BCLKX high§ D – 7 D + 4 D – 7 D + 4 ns td(BFXL-BCKXL) Delay time, BFSX low to BCLKX low¶ T – 7 T + 5 T – 7 T + 5 ns td(BCKXH-BDXV) Delay time, BCLKX high to BDX valid – 3 4 6H + 4 10H + 15 – 3 4 6H + 4 10H + 15 ns tdis(BCKXH-BDXHZ) Disable time, BDX high impedance following last data bit from BCLKX high –2 4 6H + 3 10H + 17 –2 4 6H + 3 10H + 17 ns td(BFXL-BDXV) Delay time, BFSX low to BDX valid C – 3 C + 5 4H + 2 8H + 17 C – 3 C + 5 4H + 2 8H + 17 ns † For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. ‡ T = BCLKX period = (1 + CLKGDV) * 2H C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2H when CLKGDV is even D = BCLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * 2H when CLKGDV is even § FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX and BFSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP ¶ BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (BCLKX). PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. |
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