TMS320VC5410 datasheet(22/79 Pages) TI

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TMS320VC5410

FIXEDPOINT DIGITAL SIGNAL PROCESSOR

SPRS075D – OCTOBER 1998 – REVISED MAY 2000

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

clock generator (continued)

This clock generator allows system designers to select the clock source. The sources that drive the clock

generator are:

D A crystal resonator circuit. The crystal resonator circuit is connected across the X1 and X2/CLKIN pins of

the ’VC5410 to enable the internal oscillator.

D An external clock. The external clock source is directly connected to the X2/CLKIN pin, and X1 is left

unconnected.

The software-programmable PLL features a high level of flexibility, and includes a clock scaler that provides

various clock multiplier ratios, capability to directly enable and disable the PLL, and a PLL lock timer that can

be used to delay switching to PLL clocking mode of the device until lock is achieved.Devices that have a built-in

software-programmable PLL can be configured in one of two clock modes:

D PLL mode. The input clock (X2/CLKIN) is multiplied by 1 of 31 possible ratios.

D DIV (divider) mode. The input clock is divided by 2 or 4. Note that when DIV mode is used, the PLL can be

completely disabled in order to minimize power dissipation.

The software-programmable PLL is controlled using the 16-bit memory-mapped (address 0058h) clock mode

that upon reset, the CLKMD register is initialized with a predetermined value dependent only upon the state of

the CLKMD1 – CLKMD3 pins. The CLKMD pin configured clock options are shown in Table 5.

Table 5. CLKMD Pin Configured Clock Options

CLKMD1

CLKMD2

CLKMD3

CLKMD REGISTER

RESET VALUE

CLOCK MODE

CLKMD1

CLKMD2

CLKMD3

RESET VALUE

CLOCK MODE

0000h

Divide-by-2, with external source

1000h

Divide-by-2, with external source

2000h

Divide-by-2, with external source

–

Stop mode

4000h

Divide-by-2, internal oscillator enabled

0007h

PLLx1 with external source

6000h

Divide-by-2, with external source

7000h

Reserved

enhanced external parallel interface (XIO2)

The ’VC5410 external interface has been redesigned to include several improvements, including: simplification

of the bus sequence, more immunity to bus contention when transitioning between read and write operation,

the ability for external memory access to the DMA controller, and optimization of the power-down modes.

The bus sequence on the ’VC5410 still maintains all of the same interface signals as on previous ’54x devices,

but the signal sequence has been simplified. Most external accesses now require 3 cycles composed of a

leading cycle, an active (read or write) cycle, and a trailing cycle. The leading and trailing cycles provide

additional immunity against bus contention when switching between read operations and write operations. To

maintain high-speed read access, a consecutive read mode that performs single-cycle reads as on previous

’54x devices is available.

TMS320VC5410 Datasheet(PDF) 22 Page - Texas Instruments

TMS320VC5410 Datasheet(HTML) 22 Page - Texas Instruments

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