TMS320VC5410 datasheet(25/79 Pages) TI

25 / 79 page

TMS320VC5410

FIXEDPOINT DIGITAL SIGNAL PROCESSOR

SPRS075D – OCTOBER 1998 – REVISED MAY 2000

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

enhanced external parallel interface (XIO2) (continued)

Figure 10 shows the bus sequence for all memory writes and I/O writes. The accesses shown in Figure 10

always require 3 CLKOUT cycles to complete.

WRITE

CLKOUT

A[22:0]

D[15:0]

R/W

PS/DS/IS

Leading

Cycle

Write

Cycle

MSTRB or IOSTRB

Trailing

Cycle

Figure 10. Memory Write and I/O Write Bus Sequence

The enhanced interface also provides the ability for DMA transfers to extend to external memory. For more

information on DMA capability, see the DMA sections that follow.

The enhanced interface improves the low-power performance already present on the ’C5000 family by

switching off the internal clocks to the interface when it is not being used. This power-saving feature is automatic,

requires no software setup, and causes no latency in the operation of the interface.

Additional features integrated in the enhanced interface are the ability to automatically insert bank-switching

cycles when crossing 32K memory boundaries (see the “programmable bank-switching” section), the ability to

program up to 14 wait states through software (see the “software-programmable wait-state generator” section),

and the ability to divide down CLKOUT by a factor of 1, 2, 3, or 4. Dividing down CLKOUT provides an alternative

to wait states when interfacing to slower external memory or peripheral devices. While inserting wait states

extends the bus sequence during read or write accesses, it does not slow down the bus signal sequences at

the beginning and the end of the access. Dividing down CLKOUT provides a method of slowing the entire bus

sequence when necessary. The CLKOUT divide-down factor is controlled through the DIVFCT field in the

bank-switching control register (BSCR).

TMS320VC5410 Datasheet(PDF) 25 Page - Texas Instruments