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TMS320VC5410 Datasheet(PDF) 29 Page - Texas Instruments |
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TMS320VC5410 Datasheet(HTML) 29 Page - Texas Instruments |
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29 / 79 page ![]() TMS320VC5410 FIXEDPOINT DIGITAL SIGNAL PROCESSOR SPRS075D – OCTOBER 1998 – REVISED MAY 2000 29 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 DMA interrupts The ability of the DMA to interrupt the CPU based on the status of the data transfer is configurable and is determined by the IMOD and DINM bits in the DMA channel mode control register (DMMCRn). The available modes are shown in Table 6. Table 6. DMA Interrupts MODE DINM IMOD INTERRUPT ABU (non-decrement) 1 0 At full buffer only ABU (non-decrement) 1 1 At half buffer and full buffer Multi-Frame 1 0 At block transfer complete (DMCTRn = DMSEFCn[7:0] = 0) Multi-Frame 1 1 At end of frame and end of block (DMCTRn = 0) Either 0 X No interrupt generated Either 0 X No interrupt generated |
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