TMS320VC5410 datasheet(17/79 Pages) TI

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TMS320VC5410

FIXEDPOINT DIGITAL SIGNAL PROCESSOR

SPRS075D – OCTOBER 1998 – REVISED MAY 2000

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

programmable bank-switching

Programmable bank-switching logic allows the ’VC5410 to switch between external memory banks without

requiring external wait states for memories that need additional time to turn off. The bank-switching logic

automatically inserts one cycle when accesses cross a 32K-word memory-bank boundary inside program or

data space.

Bank-switching is defined by the bank-switching control register (BSCR), which is memory-mapped at

address 0029h. The bit fields of the BSCR are shown in Figure 6 and are described in Table 4.

CONSEC

DIVFCT

IACKOFF

Rsvd

HBH

R/W

Rsvd

BSCR (0x29)

R = Read, W = Write

Figure 6. Bank-Switching Control Register (BSCR)

Table 4. Bank-Switching Control Register Fields

BIT

NAME

RESET

VALUE

FUNCTION

Consecutive bank-switching. Specifies the bank-switching mode.

CONSEC†

CONSEC = 0

Bank-switching on 32K bank boundaries only. This bit is cleared if fast access is desired for

continuous memory reads (i.e., no starting and trailing cycles between read cycles).

CONSEC†

CONSEC

consecutive bank switches on external memory reads. Each read cycle consists of 3 cycles:

CONSEC = 1

consecutive bank switches on external memory reads. Each read cycle consists of 3 cycles:

starting cycle, read cycle, and trailing cycle.

CLKOUT output divide factor. The CLKOUT output is driven by an on-chip source having a frequency

equal to 1/(DIVFCT+1) of the DSP clock.

13 14

DIVFCT

DIVFCT = 00

CLKOUT is not divided.

13–14

DIVFCT

DIVFCT = 01

CLKOUT is divided by 2 from the DSP clock.

DIVFCT = 10

CLKOUT is divided by 3 from the DSP clock.

DIVFCT = 11

CLKOUT is divided by 4 from the DSP clock (default value following reset).

IACK signal output off. Controls the output of the IACK signal. IACKOFF is set to 1 at reset.

IACKOFF

IACKOFF = 0

The IACK signal output off function is disabled.

IACKOFF

IACKOFF = 1

The IACK signal output off function is enabled.

11–3

Rsvd

–

Reserved

HPI bus holder. Controls the HPI bus holder. HBH is cleared to 0 at reset

HBH

HBH = 0

The bus holder is disabled.

HBH

HBH = 1

The bus holder is enabled. When not driven, the HPI data bus, HD[7:0] is held in the previous

logic level.

Bus holder. Controls the bus holder. BH is cleared to 0 at reset.

BH = 0

The bus holder is disabled.

BH = 1

The bus holder is enabled. When not driven, the data bus, D[15:0] is held in the previous logic

level.

Rsvd

–

Reserved

† For additional information, see the “enhanced external parallel interface (XIO2)” section of this document.

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