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TMS320VC5410 Datasheet(PDF) 32 Page - Texas Instruments |
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TMS320VC5410 Datasheet(HTML) 32 Page - Texas Instruments |
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32 / 79 page  TMS320VC5410 FIXEDPOINT DIGITAL SIGNAL PROCESSOR SPRS075D – OCTOBER 1998 – REVISED MAY 2000 32 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 Table 8. Peripheral Memory-Mapped Registers (Continued) NAME TYPE DESCRIPTION SUB-ADDRESS ADDRESS XCR20 39h 05h McBSP0 transmit control register 2 McBSP #0 SRGR10 39h 06h McBSP0 sample rate generator register 1 McBSP #0 SRGR20 39h 07h McBSP0 sample rate generator register 2 McBSP #0 MCR10 39h 08h McBSP0 multichannel register 1 McBSP #0 MCR20 39h 09h McBSP0 multichannel register 2 McBSP #0 RCERA0 39h 0Ah McBSP0 receive channel enable register partition A McBSP #0 RCERB0 39h 0Bh McBSP0 receive channel enable register partition B McBSP #0 XCERA0 39h 0Ch McBSP0 transmit channel enable register partition A McBSP #0 XCERB0 39h 0Dh McBSP0 transmit channel enable register partition B McBSP #0 PCR0 39h 0Eh McBSP0 pin control register McBSP #0 — 3Ah–3Fh — Reserved DRR21 40h — McBSP1 Data receive register 2 McBSP #1 DRR11 41h — McBSP1 Data receive register 1 McBSP #1 DXR21 42h — McBSP1 Data transmit register 2 McBSP #1 DXR11 43h — McBSP1 Data transmit register 1 McBSP #1 — 44h–47h — Reserved SPSA1 48h — McBSP1 sub-address register McBSP #1 SPCR11 49h 00h McBSP1 serial port control register 1 McBSP #1 SPCR21 49h 01h McBSP1 serial port control register 2 McBSP #1 RCR11 49h 02h McBSP1 receive control register 1 McBSP #1 RCR21 49h 03h McBSP1 receive control register 2 McBSP #1 XCR11 49h 04h McBSP1 transmit control register 1 McBSP #1 XCR21 49h 05h McBSP1 transmit control register 2 McBSP #1 SRGR11 49h 06h McBSP1 sample rate generator register 1 McBSP #1 SRGR21 49h 07h McBSP1 sample rate generator register 2 McBSP #1 MCR11 49h 08h McBSP1 multichannel register 1 McBSP #1 MCR21 49h 09h McBSP1 multichannel register 2 McBSP #1 RCERA1 49h 0Ah McBSP1 receive channel enable register partition A McBSP #1 RCERB1 49h 0Bh McBSP1 receive channel enable register partition B McBSP #1 XCERA1 49h 0Ch McBSP1 transmit channel enable register partition A McBSP #1 XCERB1 49h 0Dh McBSP1 transmit channel enable register partition B McBSP #1 PCR1 49h 0Eh McBSP1 pin control register McBSP #1 — 4Ah–53h — Reserved DMPREC 54h — DMA channel priority and enable control register DMA DMSBAR 55h — DMA channel sub-address register DMA DMSRC0 56h/57h† 00h DMA channel 0 source address register DMA DMDST0 56h/57h† 01h DMA channel 0 destination address register DMA DMCTR0 56h/57h† 02h DMA channel 0 element count register DMA DMSFC0 56h/57h† 03h DMA channel 0 sync select and frame count register DMA DMMCR0 56h/57h† 04h DMA channel 0 transfer mode control register DMA DMSRC1 56h/57h† 05h DMA channel 1 source address register DMA † Accesses to address 56h update the sub-addressed register and post-increment the sub-address contained in DMSBAR. Accesses to 57h update the sub-addressed register without modifying DMSBAR. memory-mapped registers (continued) |
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