TMS320VC5421 datasheet(34/88 Pages) TI

34 / 88 page

TMS320VC5421

DIGITAL SIGNAL PROCESSOR

SPRS098 – DECEMBER 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

DMA accesses to external memory (continued)

DMA_ARB

CPU_ARB

EMIF

Controller

GRANT

DMA_REQ_B

DMA_GRANT_B

XDMA

(DSP

Subsystem B)

XIO

Grant

XIO

Req

Core

SEL=1

VCC

GPIO Control

(DSP Subsystem B)

54x cLEAD CPU

(DSP Subsystem B)

Req

Grant

XIO

SEL=0

Core

54x cLEAD CPU

DMA_REQUEST

GRANT_A

GPIO Control

(DSP Subsystem A)

Subsystem A)

(DSP

XDMA

DMA_REQ_A

DMA_GRANT_A

DMA_REQUEST

GRANT_B

SEL

XIO

XHOLD

XHOLDA

XDMA

XCPU

XDMA

XCPU

Figure 15. Arbitration Between XIO and xDMA for External Access

The HM bit in the ST1 indicates whether the processor continues internal execution when acknowledging an

active HOLD signal.

D HM = 0, the processor continues execution from internal program memory but places its external interface

in the high-impedance state.

D When HM = 1, the processor halts internal execution.

To ensure that proper arbitration occurs, the HM bit should be set to 0 in the memory-mapped ST1 registers

for both CPUs.

To allow the DMA access to extended data pages, the SLAXS and DLAXs bits are added to the DMMCRn

TMS320C54x DSP Reference Set, Volume 5: Enhanced

Peripherals (literature number SPRU302).

9876

43210

AUTO

INIT

DINM

IMOD

MOD

SLAXS

SIND

DMS

DLAXS

DIND

DMD

Figure 16. DMA Transfer Mode Control Register (DMMCRn)

TMS320VC5421 Datasheet(PDF) 34 Page - Texas Instruments

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