TMS320VC5421 datasheet(25/88 Pages) TI

25 / 88 page

TMS320VC5421

DIGITAL SIGNAL PROCESSOR

SPRS098 – DECEMBER 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

HPI16 memory map (continued)

Some of the features of the HPI16 include:

D 16-bit bidirectional data bus

D Multiple data strobes and control signals to allow glueless interfacing to a variety of hosts

D Multiplexed and nonmultiplexed address/data modes

D 18-bit address bus used in nonmultiplexed mode to allow access to all internal memory (including internal

extended address pages)

D 18-bit address register used in multiplexed mode. Includes address autoincrement feature for faster

accesses to sequential addresses

D Interface to on-chip DMA module to allow access to entire internal memory space

D HRDY signal to hold off host accesses due to DMA latency

D Control register available in multiplexed mode only. Accessible by either host or DSP to provide host/DSP

interrupts, extended addressing, and data prefetch capability

D Maximum data rate of 33 megabytes per second (MBps) at 100-MHz DSP clock rate (no other DMA

channels active)

The HPI16 acts as a slave to a 16-bit host processor and allows access to the on-chip memory of the DSP. There

are two modes of operation as determined by the HMODE signal:

multiplexed mode and nonmultiplexed mode.

HPI multiplexed mode

multiplexed mode, HPI16 operation is very similar to that of the standard 8-bit HPI, which is available with

other ’C54x products. A host with a multiplexed address/data bus can access the HPI16 data register (HPID),

address register (HPIA), or control register (HPIC) via the HD bidirectional data bus. The host initiates the

access with the strobe signals (HDS1, HDS2, HCS) and controls the type of access with the HCNTL, HR/W,

and HAS signals. The DSP can interrupt the host via the HINT signal, and can stall host accesses via the HRDY

signal.

host/DSP interrupts

multiplexed mode, the HPI16 offers the capability for the host and DSP to interrupt each other through the

HPIC register.

For host-to-DSP interrupts, the host must write a “1” to the DSPINT bit of the HPIC register. This generates an

interrupt to the DSP. This interrupt can also be used to wake the DSP from any of the IDLE 1,2, or 3 states. Note

that the DSPINT bit is always read as “0” by both the host and DSP. The DSP cannot write to this bit (see

Figure 7).

For DSP-to-host interrupts, the DSP must write a “1” to the HINT bit of the HPIC register to interrupt the host

via the HINT pin. The host acknowledges and clears this interrupt by also writing a “1” to the HINT bit of the HPIC

TMS320VC5421 Datasheet(PDF) 25 Page - Texas Instruments