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TMS320VC5421 Datasheet(PDF) 78 Page - Texas Instruments |
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TMS320VC5421 Datasheet(HTML) 78 Page - Texas Instruments |
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78 / 88 page  TMS320VC5421 DIGITAL SIGNAL PROCESSOR SPRS098 – DECEMBER 1999 78 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 HPI16 timing switching characteristics over recommended operating conditions†‡§ [H = 0.5tc(CO)] (see Figure 46 and Figure 53) PARAMETER MIN MAX UNIT td(DSL-HDD) Delay time, DS low to HD driven§ 3 20 ns Case 1a: Memory accesses when DMAC is active in 16-bit mode and tw(DSH) < 18H 18H+20 – tw(DSH) Case 1b: Memory accesses when DMAC is active in 16-bit mode and tw(DSH) ≥ 18H 20 td(DSL HDV1) Delay time, DS low to HD valid for first Case 1c: Memory access when DMAC is active in 32-bit mode and tw(DSH) < 26H 26H+20 – tw(DSH) ns td(DSL-HDV1) Delay time, DS low to HD valid for first byte of an HPI read Case 1d: Memory access when DMAC is active in 32-bit mode and tw(DSH) ≥ 26H 20 ns Case 2a: Memory accesses when DMAC is inactive and tw(DSH) < 10H 10H+20 – tw(DSH) Case 2b: Memory accesses when DMAC is inactive and tw(DSH) ≥ 10H 20 Case 3: Register accesses 20 td(DSL-HDV2) Multiplexed reads with autoincrement. Prefetch completed. 3 20 ns No DMA channel active 12H+5 t Delay time, DS high to HRDY high§ One or more 16-bit DMA channels active 18H+5 ns td(DSH-HYH) Delay time, DS high to HRDY high§ (writes and autoincrement reads) One or more 32-bit DMA channels active 26H+5 Writes to DSPINT and HINT 4H + 5 tv(HYH-HDV) Valid time, HD valid after HRDY high 7 ns th(DSH-HDV)R Hold time, HD valid after DS rising edge, read§ 0 10 ns td(COH-HYH) Delay time, CLKOUT rising edge to HRDY high 5 ns td(DSL-HYL) Delay time, HDS low to HRDY low§ 12 ns td(COH–HTX) Delay time, CLKOUT rising edge to HINT change 5 ns † HAD stands for HCNTL0, HCNTL1, and HR/W. ‡ HDS refers to either HDS1 or HDS2. § DS refers to the logical OR of HCS and HDS. |
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