TMS320VC5421 datasheet(12/88 Pages) TI

12 / 88 page

TMS320VC5421

DIGITAL SIGNAL PROCESSOR

SPRS098 – DECEMBER 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

Signal Descriptions (Continued)

NAME

DESCRIPTION

TYPE†

MULTICHANNEL BUFFERED SERIAL PORT 0, 1, AND 2 SIGNALS

A_BCLKR0‡§

B_BCLKR0‡§

A_BCLKR1‡§

B_BCLKR1‡§

A_BCLKR2‡§

B_BCLKR2‡§

I/O/Z

Receive clocks. BCLKR serves as the serial shift clock for the buffered serial-port receiver. Input from

an external clock source for clocking data into the McBSP. When not being used as a clock, these pins

can be used as general-purpose I/O by setting RIOEN = 1.

BCLKR can be configured as an output by the way of the CLKRM bit in the PCR register.

These pins are placed into the high-impedance state when OFF is low.

A_BCLKX0‡§

B_BCLKX0‡§

A_BCLKX1‡§

B_BCLKX1‡§

A_BCLKX2‡§

B_BCLKX2‡§

I/O/Z

Transmit clocks. Clock signal used to clock data from the transmit register. This pin can also be

configured as an input by setting the CLKXM = 0 in the PCR register. BCLKX can be sampled as an input

by way of the IN1 bit in the SPC register. When not being used as a clock, these pins can be used as

general-purpose I/O by setting XIOEN = 1.

These pins are placed into the high-impedance state when OFF is low.

A_BDR0

B_BDR0

A_BDR1

B_BDR1

A_BDR2

B_BDR2

Buffered serial data receive (input) pin. When not being used as data-receive pins, these pins can be

used as general-purpose I/O by setting RIOEN = 1.

A_BDX0

B_BDX0

A_BDX1

B_BDX1

A_BDX2

B_BDX2

O/Z

Buffered serial-port transmit (output) pin. When not being used as data-transmit pins, these pins can be

used as general-purpose I/O by setting XIOEN = 1. These pins are placed into the high-impedance state

when OFF is low.

A_BFSR0

B_BFSR0

A_BFSR1

B_BFSR1

A_BFSR2

B_BFSR2

I/O/Z

Frame synchronization pin for buffered serial-port input data. The BFSR pulse initiates the receive-data

process over the BDR pin. When not being used as data-receive synchronization pins, these pins can

be used as general-purpose I/O by setting RIOEN = 1. These pins are placed into the high-impedance

state when OFF is low.

A_BFSX0

B_BFSX0

A_BFSX1

B_BFSX1

A_BFSX2

B_BFSX2

I/O/Z

Buffered serial-port frame synchronization pin for transmitting data. The BFSX pulse initiates the

transmit-data process over the BDX pin. If RS is asserted when BFSX is configured as output, then

BFSX is turned into input mode by the reset operation. When not being used as data-transmit

synchronization pins, these pins can be used as general-purpose I/O by setting XIOEN = 1. These pins

are placed into the high-impedance state when OFF is low.

HOST-PORT INTERFACE (HPI) SIGNALS

PRIMARY

HA[17:0]

PPA[17:0]

These pins are multiplexed with the external interface pins and are used by the

HPI when the subsystem is in HPI mode (XIO = 0, MP/MC = 0).

See the PPA signal descriptions. These pins are placed into the high-impedance

state when OFF is low.

† I = Input, O = Output, S = Supply, Z = High Impedance

‡ This pin has an internal pullup resistor.

§ These pins are Schmitt triggered inputs.

¶ This pin has an internal bus holder controlled by way of the BSCR register in 54x cLEAD core of DSP subsystem A .

# This pin is used by Texas Instruments for device testing and should be left unconnected.

|| This pin has an internal pulldown resistor.

TMS320VC5421 Datasheet(PDF) 12 Page - Texas Instruments

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