TMS370 datasheet(31/63 Pages) TI

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TMS370CxCx

8-BIT MICROCONTROLLER

SPNS040B – NOVEMBER 1995 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

serial communications interface 2 module (continued)

Bit 6

TX EMPTY (SCI transmitter empty)

This bit indicates the status of the transmitter-shift register and the TXBUF register. TX EMPTY

is set to 1 by an SCI SW RESET or by a system reset.

0 = The CPU has written data to the TXBUF register; the data has not been completely

transmitted.

1 = TXBUF and TXSHF registers are empty.

Bit 7

TXRDY (SCI transmitter ready)

The TXRDY bit is set by the transmitter to indicate that TXBUF is ready to receive another

character. The bit is automatically cleared when a character is loaded into TXBUF. This flag

asserts a transmitter interrupt if the interrupt-enable bit SCI TX INT ENA (TXCTL.0) is set. TXRDY

is a read-only flag. It is set to 1 by an SCI SW RESET or by a system reset.

0 = TXBUF is full.

1 = TXBUF is ready to receive a character.

SCI receiver interrupt control and status register (RXCTL)

The RXCTL register contains one interrupt-enable bit and seven receiver-status flags (two of which can generate

interrupt requests). The status flags are updated each time a complete character is transferred to the RXBUF.

They are cleared each time RXBUF is read.

Table 22. SCI Receiver Interrupt Control and Status Register (RXCTL) [Memory Address – 1055h]

Bit #

P055

RX ERROR

RXRDY

BRKDT

RXWAKE

SCI RX

INT ENA

R–0

RW – 0

R = read, W = write, –

n = value of the bit after the register is reset

Bit 0

SCI RX INT ENA (SCI receiver interrupt enable)

The SCI RX INT ENA bit controls the ability of the RXRDY and the BRKDT bits to request an

interrupt but does not prevent these flags from being set.

0 = Disables RXRDY/BRKDT interrupt

1 = Enables RXRDY/BRKDT interrupt

Bit 1

RXWAKE (receiver wake-up detect)

The SCI sets this bit when a receiver wake-up condition is detected. In the address bit

multiprocessor mode, RXWAKE reflects the value of the address bit for the character contained

in RXBUF. In the idle line multiprocessor mode, RXWAKE is set if an idle SCIRXD line is detected.

RXWAKE is a read-only flag. It is cleared by transfer of the first byte after the address byte to

RXBUF, by reading the address character in RXBUF, by an SCI SW RESET, or by a system reset.

Bit 2

PE (SCI parity error flag)

This flag bit is set when a character is received with a mismatch between the number of 1s and

its parity bit. The parity checker includes the address bit in the calculation. If parity generation and

detection are not enabled, the PE flag is disabled and read as 0. The PE bit is reset by an SCI SW

RESET, by a system reset, or by reading RXBUF.

0 = No parity error or parity is disabled

1 = Parity error detected

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