TMS370 datasheet(39/63 Pages) TI

39 / 63 page

TMS370CxCx

8-BIT MICROCONTROLLER

SPNS040B – NOVEMBER 1995 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

analog-to-digital converter 2 module (continued)

Table 31. A / D Control Register (ADSTAT)

Bit #

P071

—

READY

AD INT

FLAG

AD INT

ENA

R–0

RC – 0

RW – 0

R = read, W = write, C = clear only, –

n = value of the bit after the register is reset

Bit 0

AD INT ENA (A / D interrupt enable)

This bit controls the ADC2 module’s ability to generate an interrupt.

0 = Disable A/D interrupt

1 = Enable A/D interrupt

Bit 1

AD INT FLAG (A/D interrupt flag)

The ADC2 module sets this bit at the end of an ADC2 conversion. If this bit is set while the A/D

INT ENA bit is set, an interrupt request is generated. Clearing this flag clears pending A/D interrupt

requests. This bit is cleared by the system reset or by entering HALT or STANDBY mode. Software

cannot set this bit.

Bit 2

AD READY (A/D converter ready)

The ADC2 module sets this bit whenever a conversion is not in progress and the ADC2 is ready

for a new conversion to start. Writing to this bit has no effect on its state.

0 = Conversion is in process

1 = Converter is ready

Bits 3–7

Reserved (read data is indeterminate)

Table 32. A / D Conversion Data Register (DATA)

Bit #

P072

DATA 7

DATA 6

DATA 5

DATA 4

DATA 3

DATA 2

DATA 1

DATA 0

R–0

R = read, –

n = value of the bit after the register is reset

The analog-to-digital conversion data is loaded into this register at the end of a conversion and remains until

replaced by another conversion.

Table 33. AN0–AN3 Port E0 – E3 Data Input Register (ADIN)

Bit #

P07D

—

DATA IN

AN3

DATA IN

AN2

DATA IN

AN1

DATA IN

AN0

R–0

R = read, –

n = value of the bit after the register is reset

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