TMS370 datasheet(32/63 Pages) TI

32 / 63 page

TMS370CxCx

8-BIT MICROCONTROLLER

SPNS040B – NOVEMBER 1995 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

serial communications interface 2 module (continued)

Bit 3

OE (SCI overrun error flag)

The SCI sets this bit when a character is transferred into RXBUF before the previous character

has been read out. The previous character is overwritten and lost. The OE flag is reset by an SCI

SW RESET, by a system reset, or by reading RXBUF.

0 = No overrun error detected

1 = Overrun error detected

Bit 4

FE (SCI framing error flag)

The SCI sets this bit when it does not find a stop bit that it expects. Only the first stop bit is checked.

The missing stop bit indicates that synchronization with the start bit has been lost and that the

character is incorrectly framed. It is reset by an SCI SW RESET, by a system reset, or by reading

RXBUF.

0 = No framing error detected

1 = Framing error detected

Bit 5

BRKDT (SCI break detect flag)

The SCI sets this bit when a break condition occurs. A break condition occurs when the SCIRXD

line remains continuously low for at least 10 bits, beginning after a missing first stop bit. The

occurrence of a break causes a receiver interrupt to be generated if the SCI RX INT ENA bit is

a 1, but it does not cause the receiver buffer to be loaded. A BRKDT interrupt can occur, even if

the receiver SLEEP bit is set to 1.

BRKDT is cleared by an SCI SW RESET or by a system reset. It is not cleared by receipt of a

character after the break is detected. In order to receive more characters, the SCI must be reset

by toggling the SCI SW RESET bit or by a system reset.

Bit 6

RXRDY (SCI receiver ready)

The receiver sets this bit to indicate that RXBUF is ready with a new character and clears the bit

when the character is read. A receiver interrupt is generated if the SCI RX INT ENA bit is a 1.

RXRDY is reset by an SCI SW RESET or by a system reset.

Bit 7

RX ERROR (SCI receiver error flag)

The RX ERROR flag indicates that one of the error flags in the receiver status register is set. It

is a logical OR of the parity, overrun, framing error, and break detect flags. The bit can be used

for fast error condition checking during the interrupt service routine because a negative value of

the status register indicates that an error condition has occurred. This error flag cannot be cleared

directly but is cleared if no individual error flags are set. This bit is cleared by an SCI SW RESET,

by a system reset, or by reading RXBUF.

TMS370 Datasheet(PDF) 32 Page - Texas Instruments

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