TMS370 datasheet(4/63 Pages) TI

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TMS370CxCx

8-BIT MICROCONTROLLER

SPNS040B – NOVEMBER 1995 – REVISED FEBRUARY 1997

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

description (continued)

Table 1 provides a memory configuration overview of the TMS370CxCx devices.

Table 1. Memory Configurations

DEVICES

PROGRAM MEMORY

(BYTES)

DATA MEMORY

(BYTES)

PACKAGES

28-PIN LCC OR DIP

ROM

EPROM

RAM

EEPROM

28-PIN LCC OR DIP

TMS370C3C0A

—

128

—

FN – PLCC

N – PDIP

TMS370C6C2A

—

128

—

FN – PLCC

N – PDIP

SE370C6C2A†

—

128

—

FZ – CLCC

JD – CDIP

† System evaluators and development are for use only in prototype environment, and their reliability has not been characterized.

The suffix letter (A) appended to the device name (shown in Table 1) indicates configuration of the device. ROM

or EPROM devices have different configurations as indicated in Table 2. ROM devices with the suffix letter A

are configured through a programmable contact during manufacture.

Table 2. Suffix Letter Configuration

DEVICE

WATCHDOG TIMER

CLOCK

LOW-POWER MODE

EPROM A

Standard

Divide-by-4 (standard oscillator)

Enabled

Standard

Di id b 4

ROM A

Hard

Divide-by-4 or

Divide-by-1 (PLL)

Enabled or disabled

Simple

Divide-by-1 (PLL)

The 4K bytes of mask-programmable ROM in the associated TMS370C3C0A device are replaced in the

TMS370C6C2A with 8K bytes of EPROM while all other available memory and on-chip peripherals are identical.

The one-time programmable (OTP) (TMS370C6C2A) and reprogrammable (SE370C6C2A) devices are

available.

TMS370C6C2A OTP devices are available in plastic packages. This microcontroller is effective to use for

immediate production updates for other members of the TMS370C3C0A or for low-volume production runs

when the mask charge or cycle time for the low-cost mask ROM devices is not practical.

The SE370C6C2A has a windowed ceramic package to allow reprogramming of the program EPROM memory

during the development-prototyping phase of design. The SE370C6C2A devices allow quick updates to

breadboards and prototype systems during initial design iterations.

The TMS370CxCx family provides two low-power modes (STANDBY and HALT) for applications where

low-power consumption is critical. Both modes stop all CPU activity, that is, no instructions are executed. In the

STANDBY mode, the internal oscillator and the general-purpose timer remain active. In the HALT mode, all

device activity is stopped. The device retains all RAM data and peripheral configuration bits throughout both

low-power modes.

The TMS370CxCx features advanced register-to-register architecture that allows direct arithmetic and logical

operations without requiring an accumulator (for example, ADD R24, R47; add the contents of register 24 to

the contents of register 47 and store the result in register 47). The TMS370CxCx family is fully instruction-set

compatible, providing easy transition between members of the TMS370 8-bit microcontroller family.

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