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TPS2216ADAP Datasheet(PDF) 7 Page - Texas Instruments |
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TPS2216ADAP Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 27 page  TPS2214A, TPS2216A LOW-COST DUAL-SLOT PC CARD POWER SWITCH FOR SERIAL PCMCIA CONTROLLERS SLVS267 – DECEMBER 1999 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 switching characteristics PARAMETER† LOAD CONDITION† TEST CONDITIONS† MIN TYP MAX UNIT ‡ CL(xVCC) = 0.1 µF, CL(xVPP) = 0.1 µF, VO(xVCC) 1 t Output rise times‡ L(xVPP) µ , IO(xVCC) = 0§, IO(xVPP) = 0§ VO(xVPP) 0.8 ms tr Output rise times‡ CL(xVCC) = 150 µF, CL(xVPP) = 10 µF, VO(xVCC) 1.2 ms L(xVPP) µ , IO(xVCC) = 1 A, IO(xVPP) = 50 mA VO(xVPP) 2.5 ‡ CL(xVCC) = 0.1 µF, CL(xVPP) = 0.1 µF, VO(xVCC) 0.01 tf Output fall times‡ L(xVPP) µ , IO(xVCC) = 0§, IO(xVPP) = 0§ VO(xVPP) 0.01 ms tf Output fall times‡ CL(xVCC) = 150 µF, CL(xVPP) = 10 µF, VO(xVCC) 3 ms L(xVPP) µ , IO(xVCC) = 1 A, IO(xVPP) = 50 mA VO(xVPP) 8 ‡ Latch ↑ to xVPP (12 V) tpd(on) 3 ‡ Latch ↑ to xVPP (12 V) tpd(off) 25 ‡ Latch ↑ to xVPP (5 V) tpd(on) 0.6 ‡ Latch ↑ to xVPP (5 V) tpd(off) 8.5 ‡ Latch ↑ to xVPP (3 3 V) V 5 V tpd(on) 0.6 ‡ CL(xVCC) =0 1 µF Latch ↑ to xVPP (3.3 V), VI(5V) = 5 V tpd(off) 9 ‡ CL(xVCC) = 0.1 µF, CL(xVPP) = 0.1 µF, Latch ↑ to xVPP (3 3 V) V 0 V tpd(on) 1.4 ‡ L(xVPP) µ , IO(xVCC) = 0§, I0§ Latch ↑ to xVPP (3.3 V), VI(5V) = 0 V tpd(off) 9 ‡ IO(xVPP) = 0§ Latch ↑ to xVCC (5 V) tpd(on) 0.3 ‡ Latch ↑ to xVCC (5 V) tpd(off) 15 ‡ Latch ↑ to xVCC (3 3 V) V 5 V tpd(on) 0.2 ‡ Latch ↑ to xVCC (3.3 V), VI(5V) = 5 V tpd(off) 15 ‡ Latch ↑ to xVCC (3 3 V) V () 0V tpd(on) 0.4 t d Propagation delay‡ Latch ↑ to xVCC (3.3 V), VI(5V) = 0 V tpd(off) 15 ms tpd Propagation delay‡ Latch ↑ to xVPP (12 V) tpd(on) 4.5 ms Latch ↑ to xVPP (12 V) tpd(off) 13 Latch ↑ to xVPP (5 V) tpd(on) 3.3 Latch ↑ to xVPP (5 V) tpd(off) 8 Latch ↑ to xVPP (3 3 V) V 5 V tpd(on) 3 CL(xVCC) = 150 µF Latch ↑ to xVPP (3.3 V), VI(5V) = 5 V tpd(off) 9 CL(xVCC) = 150 µF, CL(xVPP) = 10 µF, Latch ↑ to xVPP (3 3 V) V 0 V tpd(on) 3 L(xVPP) µ , IO(xVCC) = 1 A, I50 A Latch ↑ to xVPP (3.3 V), VI(5V) = 0 V tpd(off) 9 IO(xVPP) = 50 mA Latch ↑ to xVCC (5 V) tpd(on) 1 Latch ↑ to xVCC (5 V) tpd(off) 12 Latch ↑ to xVCC (3 3 V) V 5 V tpd(on) 0.6 Latch ↑ to xVCC (3.3 V), VI(5V) = 5 V tpd(off) 12 Latch ↑ to xVCC (3 3 V) V 0 V tpd(on) 1 Latch ↑ to xVCC (3.3 V), VI(5V) = 0 V tpd(off) 12 † Refer to Parameter Measurement Information ‡ Specified by design: not tested in production. § No card inserted, assumes 0.1- µF recommended output capacitor (see Figure 32). |
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