TRF2020

SYNTHESIZER FOR GLOBAL SYSTEM

FOR MOBILE (GSM) CELLULAR TELEPHONES

SLWS020B – FEBRUARY 1995 – REVISED JANUARY 1998

23

POST OFFICE BOX 655303

PRINCIPLES OF OPERATION

test mode selection (continued)

Table 2. Test Mode Selection (continued)

V4

V3

V2

V1

V0

ROUTING TO LD TERMINAL

0

1

0

1

0

Auxiliary-1 reference clock

0

1

0

1

1

Auxiliary-2 clock reference clock

NOTE: All other binary combinations of the test mode field V not shown above are reserved for future use.

Bit 5 in the V-word is used to select an external pulse mode. In the external pulse mode, the CMOS main and

subcounters are fed externally sourced clock pulses through pin 18 instead of from the prescaler inputs as

normally operated. This mode makes testing of the internal CMOS counters easy.

speed-up switching time

main synthesizer

When the main frequency synthesizer is changed in frequency, it may be desirable to increase the loop

bandwidth for a short time in order to achieve a faster lock time. An analog switch is provided that can vary the

topography of the loop filter in order to achieve a faster loop gain. When the frequency is changed (and speed-up

operation is desired), the following actions occur:

1.

The new frequency coefficients for the main synthesizer are sent to the device over the serial bus.

2.

After the data is clocked in, the strobe is toggled to high.

3.

The positive edge of the strobe loads the new frequency into the main synthesizer prescaler (using the next

reference frequency pulse to synchronize).

4.

With loading of the main synthesizer prescaler, the speed-up mode analog switch is activated to a

low-impedance state and the speed-up mode charge-pump boost circuit is activated.

5.

The speed-up mode is maintained until the main synthesizer speed-up counter, previously loaded with field

C of Word-0, counts down to zero (0). The speed-up counter is clocked with the main synthesizer phase

detector reference frequency.

6.

With the speed-up counter reaching a terminal count of zero (0), the speed-up analog switch reverts to the

normal mode high-impedance state, and the speed-up mode charge pump boost circuit is deactivated.

auxiliary synthesizer

Because the frequency of the auxiliary synthesizers is rarely changed during normal operation, speed-up mode

occurs during the independent power enable of the auxiliary synthesizer sections as controlled by fields S and

T in Word-3. Upon the transition of these 1-bit fields from a logic zero (0) to a logic one (1), the following actions

occur:

1.

It is assumed that the proper frequency coefficients were written to the corresponding auxiliary synthesizer

prescaler field.

2.

The power enable bit for the corresponding auxiliary synthesizer is changed from a zero (0) to a one (1).

3.

The positive edge of the strobe loads Word-3, which contains the power enable bit fields (using the next

reference frequency pulse to synchronize).

4.

With the loading of Word-3, the speed-up mode charge-pump boost circuit is activated and the analog

switch is activated to a low-impedance state.