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SC120 Datasheet(PDF) 14 Page - Semtech Corporation |
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SC120 Datasheet(HTML) 14 Page - Semtech Corporation |
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14 / 21 page ![]() PRELIMINARY SC120 14 Applications Information (continued) the inductance value, the input voltage, and the on-time (D×T). Therefore, the instantaneous inductor current will be alternately larger and smaller than the average. If the average output current is sufficiently small, the minimum inductor current can reach zero during the off-state. If the energy stored in the inductor is depleted (if the induc- tor current decreases to zero) during the off-state, both FETs turn off for the remainder of the off-state. If this dis- continuous mode (DM) operation persists, the SC120 transitions to PSAVE operation. PSAVE Operation At light loads, the SC120 will operate in PSAVE mode. PSAVE mode ensures proper regulation when V IN is too close to V OUT while the output load is too small to keep the duty cycle above its minimum value. At very low output load, PSAVE mode will operate more efficiently than PWM mode. PSAVE operation is triggered by 256 consecutive cycles of DM operation in PWM mode, when the output of the P LIM amplifier falls to 0V during the off-state due to low load current. PSAVE mode requires fewer circuit resources than PWM mode. All unused circuitry is disabled to reduce quies- cent power dissipation. In PSAVE mode, the OUT pin voltage monitoring circuit remains active and the output voltage error amplifier operates as a comparator. PSAVE regulation is shown in Figure 2. When V OUT < 1.008xV REG , where V REG is the programmed output voltage, a burst of fixed-period switching occurs to boost the output voltage. The n-channel FET turns on (on-state) until the inductor current rises to approximately 240mA. Then the n-channel FET turns off and the p-channel FET turns on to transfer the inductor energy to the output capacitor and load for the duration of the off-state. This cycle repeats until V OUT > 1.018×V REG , at which point bot FETs are turned off. The output capacitor then discharges into the load until V OUT < 1.008×V REG , and the burst cycle repeats. When the output current increases above a predeter- mined level, either of two PSAVE exit conditions will force the resumption of PWM operation. The first PSAVE exit criterion is shown in Figure 2. If the PSAVE burst cycle cannot provide sufficient current to the output, the output voltage will decrease during the burst. If VOUT +0.8% +1.8% PSAVE Mode at Moderate Load PWM Mode at High Load -2% BURST OFF Higher Load Applied 0A Inductor Current Time Prog’d Voltage BURST OFF BURST PWM Mode PSAVE exit due to output decay 240mA Figure 2 — PSAVE Operation With Exit to PWM Due To Output Voltage Decay |
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