SC120 datasheet(16/21 Pages) SEMTECH

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PRELIMINARY

SC120

The Enable Pin

The EN pin is a high impedance logical input that can be

used to enable or disable the SC120 under processor

control. V

< 0.2V will disable regulation, set the LX pin in

a high-impedance state (turn off both FET switches), and

turn on an active discharge device to discharge the output

capacitor via the OUT pin. V

> 0.85V will enable the

output. The startup sequence from the EN pin is identical

to the startup sequence from the application of input

power.

Regulator Startup, Short Circuit Protection, and

Current Limits

The SC120 permits power up at input voltages from 0.85V

to 3.8V. Startup current limiting of the internal switching

n-channel and p-channel FET power devices protects

them from damage in the event of a short between OUT

and GND. As the output voltage rises, progressively less-

restrictive current limits are applied. This protection

unavoidably prevents startup into an excessive load.

To begin, the p-channel FET between the LX and OUT pins

turns on with its current limited to approximately 150mA,

the short-circuit output current. When V

OUT

approaches V

(but is still below 1.7V), the n-channel current limit is set

to 350mA (the p-channel limit is disabled), the internal

oscillator turns on (approximately 200kHz), and a fixed

75% duty cycle PWM operation begins. (See the section

PWM Operation.) When the output voltage exceeds 1.7V,

normal fixed frequency variable duty cycle PWM opera-

tion begins, with the n-channel FET’s current limited to

350mA to prevent excessive output voltage overshoot. If

the n-channel FET current limit is exceeded, the on-state

ends immediately and the off-state begins, overriding the

output voltage regulation controller. This reduces the

duty cycle on a cycle-by-cycle basis. When V

OUT

is within

2% of the programmed regulation voltage, the n-channel

FET current limit is raised to 1.2A.

Once variable duty cycle PWM operation is initiated, the

output becomes independent of V

and output regula-

tion can be maintained for V

as low as 0.7V, subject to the

maximum duty cycle and peak current limits. The duty

cycle must remain between 15% and 90% for the device

to operate within specification.

Note that startup with a regulated active load is not the

same as startup with a resistive load. The resistive load

output current increases proportionately as the output

voltage rises until it reaches programmed V

OUT

LOAD

, while

a regulated active load presents a constant load as the

output voltage rises from 0V to programmed V

OUT

. Note

also that if the load applied to the output exceeds an

applicable V

OUT

–dependent startup current limit or duty

cycle limit, the criterion to advance to the next startup

stage may not be achieved. In this situation startup may

pause at a reduced output voltage until the load is reduced

further.

Output Overload and Recovery

When in PSAVE operation, an increasing load will eventu-

ally satisfy one of the PSAVE exit criteria and regulation

will revert to PWM operation. As previously noted, the

PWM steady state duty cycle is determined by

D = 1 – (V

OUT

), but must be somewhat greater in prac-

tice to overcome dissipative losses. As the output load

increases, the dissipative losses also increase. The PWM

controller must increase the duty cycle to compensate.

Eventually, one of two overload conditions will occur,

determined by V

, V

OUT

, and the overall dissipative losses

due to the output load current. Either the maximum duty

cycle of 90% will be reached or the n-channel FET 1.2A

(nominal) peak current limit will be reached, which effec-

tively limits the duty cycle to a lower value. Above that

load, the output voltage will decrease rapidly and in

reverse order the startup current limits will be invoked as

the output voltage falls through its various voltage thresh-

olds. How far the output voltage drops depends on the

load V-I characteristics.

A reduction in input voltage, such as due to a discharging

battery, will lower the load current at which overload

occurs. Lower input voltage increases the duty cycle

required to produce a given output voltage. And lower

input voltage also increases the input current to maintain

the input power, which increases dissipative losses and

further increases the required duty cycle. Therefore an

increase in load current or a decrease in input voltage can

result in output overload.

Once an overload has occurred, the load must be

decreased to permit recovery. The conditions required for

Applications Information (continued)

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