ADF4602BCPZ datasheet(18/36 Pages) AD

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ADF4602

Rev. 0 | Page 18 of 36

I/Q Modulator

The I/Q modulator converts the transmit baseband input signals

to RF. Calibration techniques are used to maintain accurate IQ

balance and phase across frequency and environmental conditions,

thus ensuring that 3GPP carrier leakage and EVM and ACLR

requirements are met with good margin under all conditions.

The on-chip calibrations are carried out during the transmit

PLL lock time specified and are self-contained, requiring no

additional input from the user.

The modulator has an 80 dB gain control range, programmable

in 1/32 of a decibel step. The 12-bit word txpwr_set[11:0] in

referenced to a full-scale (500 mV peak differential) sine wave

signal applied to the transmit baseband inputs. To calculate the

output power when a WCDMA modulated signal with a certain

peak-to-average ratio is applied, Equation 1 should be used.

Output Power (dBm/3.84 MHz) = txpwr(dBm) − PAR(dB) (1)

where txpwr(dBm) is the txpwr_set[11:0] value converted to

dBm, and PAR is the peak-to-average ratio of the WCDMA

signal. For example, if an output power of −8 dBm is required

for a WCDMA signal with a peak-to-average ratio of 10 dB

txpwr(dBm) = −8 dBm + 10 dB = +2 dBm

The current consumption of the modulator scales with output

power. When the TX power is backed off from maximum, the

transceiver benefits from lower power dissipation.

VCO Output

The TX VCO output is fed to a tuned buffer stage and then to

the quadrature generation circuitry. The tuned buffer ensures

that minimum current and LO related noise is generated in the

VCO transport. This action is transparent to the user. The

quadrature generator creates the highly accurate phased signals

required to drive the modulator and also acts as a divide-by-2.

In low band, an additional divide-by-2 is used in the VCO

transport path, which is bypassed in high band. This is done to

minimize the VCO tuning range required to cover all the bands.

The phase accuracy of the signals is important in ensuring good

modulation quality and accurate output power. An on-chip

calibration ensures that the phased signals are exactly 90° out of

phase. This calibration runs each time the frequency is changed

or if the txpwr_set[11:0] word is written to. If the temperature

of the device changes, this calibration should be updated. To run

the calibration, the user should simply write to the txpwr_set[11:0]

word for each five degree change in temperature, or update the

value regularly (every few seconds) between WCDMA frames

or timeslots. This ensures that good EVM and accurate output

power are maintained as the temperature of the device changes.

TX Output Baluns

The baseband input, modulator, and all associated circuitry are

fully differential to maintain high signal integrity and noise

immunity. However, a differential output is not optimal for the

user because most power amplifiers (PAs) are singled-ended.

This situation would normally require additional external matching

components or a differential to single-ended SAW filter structure.

With the ADF4602, the SAW filter is not necessary, and the

required low loss balun is fully integrated, converting the diffe-

rential internal signals to a single-ended 50 Ω output, thus allowing

easy interfacing to the PA.

The high band output is available at the TXHBRF pin, and

the low band output is available at the TXLBRF pin. These are

directly connected to a 50 Ω load, if necessary, and do not

require ac-coupling.

DACS

The ADF4602 integrates two DACs that are designed to interface

to an external PA to control reference or bias nodes within the

PA. If this function is not required, the DACs are used for any

general purpose or powered down if not required.

DAC1 is a 5-bit voltage output DAC. The output range is from

2.3 V to 3.15 V (for VDD > 3.15 V). The DAC1 output stage is

supplied directly from VDD, with the capability to supply 10

mA of current to within 50 mV of VDD. For high accuracy, the

DAC reference is supplied from LDO5, which is internally

trimmed to 25 mV accuracy. The DAC1 output is set by the

PADAC1[4:0] word.

DAC2 is a 6-bit voltage output DAC with a range from 0 V to

2.8 V. LDO5 supplies both the reference voltage and full-scale

output voltage for DAC2. The output voltage is set by the

padac2_ow[5:0] word. The dacgpo_owen bit must also be set

high if control of DAC2 is required.

Both DACS are powered down by writing the code, 0x0, to the

respective control register.

GENERAL PURPOSE OUTPUTS

Four general-purpose outputs (GPOs) are provided on the

ADF4602. These are used to control PA bias modes or, more

commonly, the GPOs are used to control external RF front-end

switches in the transmit/receive path. The GPOs are simple 3 V

digital output drivers. GPO1 to GPO3 are capable of supplying

a maximum current of 2 mA, whereas GPO4 can supply up to

10 mA.

For operation of the GPOs, Bit dacgpo_owen must be set to 1.

The GPOs are then controlled via the gpo_ow[3:0] word.

RECEIVER DESCRIPTION

The ADF4602 contains a fully integrated direct conversion

receiver designed for multiband WCDMA femtocell applications.

High performance, low power consumption, and minimal external

components are the key features of the design. Figure 37 shows

a block diagram of the receiver, which consists of three LNA

blocks for multiband operation, high linearity I/Q mixers,

advanced baseband channel filtering, and a DC offset

compensation circuit.

ADF4602BCPZ Datasheet(PDF) 18 Page - Analog Devices

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