ADF4602

Rev. 0 | Page 29 of 36

SOFTWARE INITIALIZATION PROCEDURE

INITIALIZATION SEQUENCE

Table 14 shows the initialization sequence that should be used after power-up. Note that the 26 MHz reference clock must be applied to

the REFIN pin before programming begins. The default settings are described in the comments section, and some settings, such as output

frequency, gain, and GPO settings, may vary from those required in the end application of the user. The user can substitute his own

settings in these instances.

Table 14. Initialization Sequence

Step

Register1

Data

Comment

1

02

0x0003

Performs a soft reset of the ADF4602. The reset takes 50 μs, and no registers should be written to during this

period. After 50 μs, programming can continue as normal. This bit is self clearing.

If using 1.8 V logic levels, this register should be programmed to 0x0001 instead of 0x0003.

2

0.151

0xE0

Set VSUP2 to 3.1 V. See the Nonvolatile Memory (NVM) Initialization section for more details.

3

31

0x0010

Transfers non-volatile memory (NVM) contents to registers. Wait 200 μs before next programming step.

4

31

0x0000

Negate bit set in last programming step.

5

0.151

0x6F

Set VSUP2 back to 2.8 V.

6

01

0x2FDD

Enables receiver and disables transmit output. Selects TXHBRF pin as the transmit output and RXHB1 as the

receive input.

Enables all on-chip regulators.

19.2 MHz output clock is enabled, 26 MHz output clock is disabled.

If it is desired to disable the 19.2 MHz output clock, this register is programmed to 0x27DD.

7

12

0x0FA6

Default settings for mixer and LNA gain reduction steps.

8

13

0x103E

Default settings.

9

14

0xEE53

Default settings.

10

15

0x0890

Sets received gain calibration, WCDMA filter mode, and output common-mode voltage to 1.4 V.

11

21

0x001F

Default settings.

12

22

0x8000

Enables DAC and GPO manual control.

13

0.144

0x06

Default settings.

14

0.155

0x78

Default settings.

15

0.153

0x85

Default settings.

16

0.165

0x20

Default settings.

17

0.170

0xF0

Default settings.

18

0.171

0x04

If transmit synthesizer frequency is >2100 MHz

0x00

If transmit synthesizer frequency is <2100 MHz

19

0.174

0x5F

If transmit synthesizer frequency is >2100 MHz

0x50

If transmit synthesizer frequency is <2100 MHz

20

0.175

0x14

Default settings.

21

11

0x0050

Receiver gain set to 80 dB.

22

10

0x9858

Receiver synthesizer frequency set to 1950 MHz. The PLL takes 200 μs to lock. Registers should not be

written to during this period.

23

26

0xA730

Transmit synthesizer frequency set to 2140 MHz. The PLL takes 200 μs to lock. Registers should not be

written to during this period.

24

01

0x2FFD

Enables transmit output.

25

28

0xA001

Enables control of the output power and sets the txpwr_set field to 0 dBm. Control of output power is via

the txpwr_set bits.