ADF4602BCPZ datasheet(22/36 Pages) AD

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ADF4602

Rev. 0 | Page 22 of 36

FREQUENCY SYNTHESIS

The ADF4602 contains two fully integrated programmable

frequency synthesizers for generation of transmit and receive

local oscillator (LO) signals. The design uses a fractional-N

architecture for low noise and fast lock-time. The fractional-N

functionality is implemented with a third order Σ-Δ modulator.

Figure 41 shows a block diagram of the synthesizer architecture.

PFD

FREF

LOOP

FILTER

DIVIDERS

DIGITAL DECODE

RxFREQ[15:0]

50kHz STEP

÷2

LPF

VCO

FVCO: 3.4GHz TO

4.4GHz RANGE

VCO FREQ CAL

AND AMPLITUDE

CONTROL

Σ-Δ

PHASE FREQUENCY

DETECTOR AND

CHARGE PUMP

Figure 41. Frequency Synthesizer Block Diagram

All necessary components are fully integrated for both transmit

and receive synthesizers, including loop filters, VCOs, and tank

components. The VCOs run at 2× the high band frequency and

4× the low band frequency. The dividers are external to the

synthesizer loop. This minimizes VCO leakage power at the

desired frequency and tuning range requirements of the VCO.

The VCOs use a multiband structure to cover the wide

frequency range required.

The design incorporates both frequency and amplitude calibration

to ensure that the oscillator is always operating with its optimum

performance. The calibrations occur during the 200 μs PLL lock

time and are fully self contained, requiring no user inputs.

The charge pump and loop filter are internally trimmed to

remove variations associated with manufacture and frequency.

This process is fully automated.

To aid simplified programming, the ADF4602 contains a frequency

decode table for the synthesizers, meaning the programmer is

not concerned with the internal operation of the counters and

fractional-N system. Frequency step sizes of 50 kHz are possible

with both transmit and receive synthesizers. The programming

words rxfreq[15:0] and txfreq[15:0] set the frequency in

50 kHz steps from 0 MHz to 3276.75 MHz. Note that the

synthesizers do not cover this full range. The frequency range

for each synthesizer in high and low bands is given in the

Specifications section.

When the high band is enabled, the programmed frequency

is equal to the LO frequency. For low band operation, the

programmed frequency should be set to 2× the desired LO

frequency.

The transmit and receive synthesizers are enabled by setting

Bit txsynthen and Bit rxsynthen in Register 1, respectively.

Reference Path

The ADF4602 requires a 26 MHz reference frequency input.

A VCTCXO is used to provide this. The reference input is ac-

coupled internally, so external ac coupling is not necessary.

The 26 MHz reference is internally buffered and distributed to

the respective blocks, such as the synthesizer PFD inputs. Figure 42

shows a block diagram.

The ADF4602 provides two buffered outputs: a buffered version

of the 26 MHz reference on Pin REFCLK and a 19.2 MHz

WCDMA chip clock on Pin CHIPCLK. The 19.2 MHz chip

clock is a multiple of the 3.84 MHz chip rate used in WCDMA.

Thus, it can be used to clock ADCs/DACs elsewhere in the

system. The chip clock is generated by an integrated PLL and

contains no user settings.

Both outputs are slew rate limited and produce low swing digital

outputs. The buffers contain their own 1.5 V regulator circuits

to improve isolation and minimize unwanted supply noise. The

26 MHz and 19.2 MHz buffer outputs are enabled or disabled

by programming Bit refclken and Bit chipclken (Register 1).

PLL

REFIN (26MHz)

REFCLK

CHIPCLK

VSUP8

REG

1.5V

CHIPCLKEN

REFCLKEN

26MHz CLOCK

DISTRIBUTION

Figure 42. Reference Path Block Diagram

All reference sections are powered from VSUP8, which can

safely be removed from the chip in isolation, to enter a low

current power-down mode. Calibration data is not lost, but the

reference frequency ceases to exist. As soon as VSUP8 is re-

applied, oscillation begins. This is visible at the buffer outputs,

as long as they were previously enabled.

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