ADF4602BCPZ datasheet(23/36 Pages) AD

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ADF4602

Rev. 0 | Page 23 of 36

SERIAL PORT INTERFACE (SPI)

The ADF4602 contains internal registers that are used to configure

the device. The three-wire serial port interface provides read

and write access to the internal registers. For write, read

requests, and read operations, 26-bit transfers are used. The

MSB of all words are transferred first.

The read request format has the same address structure as the

write format but does not contain a data field. Padding is used

to maintain the 26-bit word length.

The readback format is the same as the word format during a

write. Again, padding is used to maintain the 26-bit word length.

Format

Table 9. SPI Chip Select Code

Figure 43 shows the format of the register write. This consists of

a 5-bit address and 16-bit data words. The exception is register

A1 = 00000, where the lower data byte is used as an 8-bit sub-

address. In total, this creates 31 16-bit registers and 256 8-bit

registers. The 31 16 bit registers are referred to in the text as

“Register 31” for example, while the 256 8-bit sub registers are

referred to as “Register 0.144”.

CS[2]

CS[1]

CS[0]

Device

ADF4602

All other permutations

Reserved

OPERATION AND TIMING

SCLK, SDATA, and SEN are used to transfer data into the

ADF4602 registers. Data is clocked into the register, MSB, first

on the rising edge of each SCLK. The data is transferred to the

selected register address on the rising edge of SEN. See Figure 2

and Figure 3 for timing information.

OP is a 2-bit code specifying the type of operation being performed

(see Table 8 for more information). The chip select code, CS,

is a 3-bit field indicating which device on the bus is being

programmed. For the ADF4602, CS should be set to 001 (D2,

D1, D0).

Read

Table 8. SPI Operation Code

Figure 3 shows a read operation. First, a read request is written

by the host to the ADF4602. SEN must remain high for at least

three SCLK periods between the read request operation and the

following read operation. The host must release the SDATA line

during this period. The ADF4602 takes control of SDATA, and the

read operation commences when the host device drives SEN low.

OP[1]

OP[0]

Operation

Description

Write

Normal register write.

Set

in the data word are set. Other

bits are not modified.

Clear

in the data word are cleared.

Other bits are not modified.

Read

The SDATA output voltage during readback is set to 1.8 V or

2.8 V. Bit sif_vsup8 (Register 2) controls this. A 0 in this bit

configures the device to use the 1.8 V VINT supply, whereas a 1

configures the 2.8 V VSUP8 supply. After power-up or after a

soft reset, the ADF4602 defaults to 2.8 V readback mode.

BIT POSITION

OPERATION

25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

WRITE

W[25:0]

WRITE

W[25:0]

READ REQUEST

Q[25:0]

READ REQUEST

Q[25:0]

READ

Q[25:0]

READ

Q[25:0]

DATA

D[15:0]

RANDOM PADDING

P[15:0]

DATA

D[7:0]

SUBADDRESS

A2[7:0]

RANDOM PADDING

P[7:0]

SUBADDRESS

A2[7:0]

DATA

D[7:0]

SUBADDRESS

A2[7:0]

DATA

D[15:0]

ADDRESS

A1[4:0]

ADDRESS

A1 = 00000

ADDRESS

A1[4:0]

ADDRESS

A1[4:0]

ADDRESS

A1 = 00000

ADDRESS

A1[4:0]

[1:0]

OP = 11

[1:0]

[2:0]

Figure 43. SPI Register Write Format

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