SN75DP120RHHT datasheet(5/27 Pages) TI

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ShutDown

Mode

LP# high

Powerup

LP#=0

Standby

Mode

LP# low

ActiveMode

CAD=0 -> DP

CAD=1 -> TMDS

D3 pwr

downmode

enterD3

AUXcmd

ExitD3

AUXcmd

HPD_SINK

LowtoHigh

transition

LP# low

HPD_SINKlow

for >tT(HPD)

HPD_SINK

High AND

AUXLink

TrainingStarted

HPD_SINKlow

for >tT(HPD)

Output

Disable

Mode

invalidDPCD

registerentry

DPCDregister

corrected

any

stat

SN75DP120

www.ti.com

SLLSE08 – OCTOBER 2009

PIN FUNCTIONS (continued)

I/O

DESCRIPTION

SIGNAL

NO.

CAD_INV

I [CMOS] w/ weak

CAD output polarity Inversion

pulldown

When CAD_INV = H; CAD_SRC is INVERSE logic of CAD_SINK

When CAD_INV = L; CAD_SRC is NON-INVERSE logic of CAD_SINK

HPD_INV

I [CMOS] w/ weak

HPD output polarity Inversion

pulldown

When HPD_INV = H; HPD_SRC is set to INVERSE logic of HPD_SINK, and HPD_SRC VOH is

fixed at 0.8V to 1.1V, i.e. not referenced to VDD

When HPD_INV = L; HPD_SRC is set to NON-INVERSE logic of HPD_SINK, and HPD_SRC

VOH is referenced to VDD

SUPPLY AND GROUND PINS

VDD

HPD_SRC (when HPD_INV = H) and CAD_SRC Supply

VCC

4, 16, 24,

3.3V Supply

28, 36

GND

1, 7, 13,

Ground

21, 32

STATUS DETECT AND OPERATING MODES FLOW DIAGRAM

The SN75DP120 switches between power saving and active modes in the following way:

Figure 1. SN75DP120 Operational Modes Flow Chart

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