LP#

HPD_SINK

0

1

0

1

HPD_SRC

0

1

MainLink

Z

0

1

DATA

LP#

HPD_SINK

0

1

0

1

HPD_SRC

0

1

MainLink

Z

0

1

HI-Z

DATA

SN75DP120

SLLSE08 – OCTOBER 2009

www.ti.com

2. HPD Interrupt and Time Out

–

In this case the HPD_SINK input is initially HIGH. The HPD_SRC output logic state will follow the state of

the HPD_SINK input (when HPD_INV = L). If the HPD_SINK input pulses LOW, as may be the case if the

Sink device is requesting an interrupt, the HPD_SRC output to the source will also pulse Low for the

same duration of time with a slight delay (see Figure 18). The delay of this signal through the

assume that an unplug event has occurred and enter the low power state (see Figure 19). Once the

HPD_SINK input goes high again the device will return to the active state as indicated in Figure 17.

Figure 18.

Figure 19.

20

Submit Documentation Feedback

Copyright © 2009, Texas Instruments Incorporated

Product Folder Link(s): SN75DP120