ATXMEGA64A1 datasheet(12/99 Pages) ATMEL

12 / 99 page

8067I–AVR–04/09

XMEGA A1

7.4.1

I/O Memory

All peripherals and modules are addressable through I/O memory locations in the data memory

space. All I/O memory locations can be accessed by the Load (LD/LDS/LDD) and Store

(ST/STS/STD) instructions, transferring data between the 32 general purpose registers in the

CPU and the I/O Memory.

The IN and OUT instructions can address I/O memory locations in the range 0x00 - 0x3F

directly.

I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and

CBI instructions. The value of single bits can be checked by using the SBIS and SBIC instruc-

tions on these registers.

The I/O memory address for all peripherals and modules in XMEGA A1 is shown in the “Periph-

eral Module Address Map” on page 55.

7.4.2

SRAM Data Memory

The XMEGA A1 devices has internal SRAM memory for data storage.

7.4.3

EEPROM Data Memory

The XMEGA A1 devices have internal EEPROM memory for non-volatile data storage. It is

addressable either in a separate data space or it can be memory mapped into the normal data

memory space. The EEPROM memory supports both byte and page access.

2000

Internal SRAM

(16 KB)

2000

Internal SRAM

(8 KB)

2000

Internal SRAM

(4 KB)

5FFF

3FFF

2FFF

6000

External Memory

(0 to 16 MB)

4000

External Memory

(0 to 16 MB)

3000

External Memory

(0 to 16 MB)

FFFFFF

Byte Address

ATxmega384A1

Byte Address

ATxmega256A1

I/O Registers

(4 KB)

I/O Registers

(4 KB)

FFF

1000

EEPROM

(4 KB)

1000

EEPROM

(4 KB)

1FFF

2000

Internal SRAM

(32 KB)

2000

Internal SRAM

(16 KB)

9FFF

5FFF

10000

External Memory

(0 to 16 MB)

6000

External Memory

(0 to 16 MB)

FFFFFF

Figure 7-2.

Data Memory Map (Hexadecimal address)

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