ATXMEGA64A1 datasheet(24/99 Pages) ATMEL

24 / 99 page

8067I–AVR–04/09

XMEGA A1

12.3.5

JTAG reset

The MCU is reset as long as there is a logic one in the Reset Register in one of the scan chains

of the JTAG system. Refer to IEEE 1149.1 (JTAG) Boundary-scan for details.

12.3.6

PDI reset

The MCU can be reset through the Program and Debug Interface (PDI).

12.3.7

Software reset

The MCU can be reset by the CPU writing to a special I/O register through a timed sequence.

12.4

WDT - Watchdog Timer

12.4.1

Features

• 11 selectable timeout periods, from 8 ms to 8s.

• Two operation modes

– Standard mode

– Window mode

• Runs from the 1 kHz output of the 32 kHz Ultra Low Power oscillator

• Configuration lock to prevent unwanted changes

12.4.2

Overview

The XMEGA A1 has a Watchdog Timer (WDT). The WDT will run continuously when turned on

and if the Watchdog Timer is not reset within a software configurable time-out period, the micro-

controller will be reset. The Watchdog Reset (WDR) instruction must be run by software to reset

the WDT, and prevent microcontroller reset.

The WDT has a Window mode. In this mode the WDR instruction must be run within a specified

period called a window. Application software can set the minimum and maximum limits for this

window. If the WDR instruction is not executed inside the window limits, the microcontroller will

be reset.

A protection mechanism using a timed write sequence is implemented in order to prevent

unwanted enabling, disabling or change of WDT settings.

For maximum safety, the WDT also has an Always-on mode. This mode is enabled by program-

ming a fuse. In Always-on mode, application software can not disable the WDT.

ATXMEGA64A1 Datasheet(PDF) 24 Page - ATMEL Corporation