 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
AD7291 Datasheet(PDF) 4 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
AD7291 Datasheet(HTML) 4 Page - Analog Devices |
|
|
4 / 21 page  AD7291 Preliminary Technical Data Rev. PrC | Page 4 of 21 I2C TIMING SPECIFICATIONS t6 t7 t2 t11 t4 t1 t12 t10 t5 t9 t6 t3 t8 SCL S SDA S = START CONDITION P = STOP CONDITION P P S Figure 2. 2-Wire Serial Interface Timing Diagram All values were measured with the input filtering enabled. CB refers to the capacitive load on the bus line, with tr and tf measured between 0.3 VDRIVE and 0.7 VDRIVE (see Figure 2) Unless otherwise noted, VDD = 2.8V to 3.6V; VDRIVE = 1.65 V to 3.6 V; VREF = 2.5 V internal/external; TA = −40°C to + 125°C, unless otherwise noted. Table 3. Limit at t MIN, tMAX Parameter Conditions Min Typ Max Unit Description fSCL Standard mode 100 kHz Serial clock frequency Fast mode 400 kHz t1 Standard mode 4 µs tHIGH, SCL high time Fast mode 0.6 µs t2 Standard mode 4.7 µs tLOW, SCL low time Fast mode 1.3 µs t3 Standard mode 250 ns tSU;DAT, data setup time Fast mode 100 ns t41 Standard mode 0 3.45 µs tHD;DAT, data hold time Fast mode 0 0.9 µs t5 Standard mode 4.7 µs tSU;STA, setup time for a repeated start condition Fast mode 0.6 µs t6 Standard mode 4 µs tHD;STA, hold time for a repeated start condition Fast mode 0.6 µs t7 Standard mode 4.7 µs tBUF, bus-free time between a stop and a start condition Fast mode 1.3 µs t8 Standard mode 4 µs tSU;STO, setup time for a stop condition Fast mode 0.6 µs t9 Standard mode 1000 ns tRDA, rise time of the SDA signal Fast mode 20 + 0.1 CB 300 ns t10 Standard mode 300 ns tFDA, fall time of the SDA signal Fast mode 20 + 0.1 CB 300 ns t11 Standard mode 1000 ns tRCL, rise time of the SCL signal Fast mode 20 + 0.1 CB 300 ns t11A Standard mode 1000 ns tRCL1, rise time of the SCL signal after a repeated Fast mode 20 + 0.1 CB 300 ns start condition and after an acknowledge bit t12 Standard mode 300 ns tFCL, fall time of the SCL signal Fast mode 20 + 0.1 CB 300 ns tSP Fast mode 0 50 ns Pulse width of the suppressed spike tPOWER-UP 0.6 µs Power-up and acquisition time 1 A device must provide a data hold time for SDA in order to bridge the undefined region of the SCL falling edge. |
|
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
