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AD7291

Preliminary Technical Data

Rev. PrC | Page 13 of 21

Table 10. Channel Selection bits for Command Register

D15

D14

D13

D12

D11

D10

Selected Analog Input Channel

Comments

No channel selected

If more than one channel is

selected, the AD7291

converts the selected sequence of

channels starting with the lowest

channel in the sequence.

Convert on Channel 8 (VIN8)

Convert on Channel 7 (VIN7)

Convert on Channel 6 (VIN6)

Convert on Channel 5 (VIN5)

Convert on Channel 4 (VIN4)

Convert on Channel 3 (VIN3)

Convert on Channel 2 (VIN2)

Convert on Channel 1 (VIN1)

Table 11. TSENSE Data Format

Input

D11(MSB)

D10

D0 (LSB)

Value (°C)

−512

+256

+128

+64

+32

+16

+0.5

+0.25

Sample Delay and Bit Trial Delay

It is recommended that no I2C bus activity occur when a

conversion is taking place; however, this may not be possible,

for example, when operating in autocycle mode. Bit D5 in the

configuration register is used to delay critical sample intervals

and bit trials from occurring while there is activity on the I2C

bus. This results in a quiet period for each bit decision. On

power up, Bit[D5] is disabled and the bit trial-and-sample

interval delaying mechanism is not implemented. It is

recommended to enabled this bit in the command register to

ensure the conversion results are less susceptible to interference

from external noise. To enable this functionality write a 1 to the

respective bit in the command register. When enabled, the

AD7291 delays the bit trials from occurring when there is

activity on the I2C bus, thus ensuring good dc linearity

performance by reducing the glitch noise seen by the converter.

In applications where ac rather than dc performance is critical,

this function can be disabled to ensure the sampling point is

fixed as this feature may introduce excessive jitter, degrading

the SNR for large signals above 300 Hz. In cases where there is

excessive activity on the interface lines, enabling these bits may

cause the overall conversion time to increase.

The AD7291 also incorporates functionality that allows it to

reject glitches shorter than 50 ns. This feature improves the

noise susceptibility of the device.

VOLTAGE CONVERSION RESULT REGISTER (0X01)

The conversion result register is a 16-bit read-only register that

stores the conversion result from the ADC in straight binary

format. A 2-byte read is necessary to read data from this

second bytes of data to be read from AD7291. Each AD7291

conversion result consists of four channel address bits (see Table

14) and the 12-bit data result. Bit D15 to Bit D12 are the

channel address bits which identifies the ADC channel that

corresponds to the subsequent result. Bit D11 to Bit D0 contain

the most recent ADC result.

Table 12. Conversion Value Register (First Read)

D15

D14

D13

D12

D11

D10

ADD3

ADD2 ADD1

ADD0 B11

(MSB)

B10

Table 13. Conversion Value Register (Second Read)

Table 14. Channel Address bits for Result Register

ADD2

ADD1

ADD0

Analog Input Channel

VIN1

VIN2

VIN3

VIN4

VIN5

VIN6

VIN7

VIN8

TSENSE

TSENSE average result

Temperature Value Format

The temperature reading from the ADC is stored in an 11-bit

twos complement format, D11 to D0, to accommodate both

positive and negative temperature measurements. The

temperature data format is provided in Table 11.

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