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AD7291

Preliminary Technical Data

Rev. PrC | Page 16 of 21

MODES OF OPERATION

When supplies are first applied to the AD7291, the ADC powers

up in partial power down mode and normally remains in this

partial power down state while not converting. Once the master

addresses the AD7291 it exits partial power down. There are

two methods of initiating a conversion on the AD7291,

Command mode and Autocycle mode.

COMMAND MODE

In command mode, the AD7291 ADC converts on-demand on

either a single channel or a sequence of channels. Writing in the

command register puts the part into command mode. This is

the default mode of operation and allows a conversion to be

automatically selected any time a write operation occurs to the

Command Register. To enter this mode, the required

combination of channels is written into the command register

(0x00). Following the write operation, the AD7291 must be

addressed again to indicate that a read operation is required.

The read then takes place from the voltage or temperature

conversion result register. For the first conversion to occur the

address pointer written to the AD7291 must points to the

Voltage or Temperature Conversion Result Register. The

conversion is completed while the first four Channel Address

bits are read. The next conversion in the sequence takes place,

once the next read from the result register is initiated. The

acquisition and conversion times combined should take

approximately 3 µs. When in command mode, the part cycles

through the selected channels from the lowest selected channel

in the sequence to the next lowest until all the channels in the

sequence are converted.

To exit the command mode, the master should not acknowledge

the final byte of data. This stops the AD7291 transmitting,

allowing the master to assert a stop condition on the bus. On

the receipt of a STOP condition, the AD7291 stops converting

and enters partial power down mode, but the content of the

command register is preserved. Once the part is readdress and a

read initiated from the Voltage Conversion Register the AD7291

will begin converting on the previously selected sequence of

channels. The conversion sequence will starting converting the

first selected channel in the sequence That is, if Channel 1, 2

and 3 are selected and a STOP condition occurs after Channel

1’s result is read, on resumption of conversions Channel 1 will

be reconverted and the conversion sequence will continue.

The example in Figure 10 shows the command mode

converting on a sequence of channels including VIN1, VIN2, and

VIN3

1. The master device asserts a start condition on SDA.

2. The master sends the 7-bit slave address followed by the

write bit (low).

3. The addressed slave device (AD7291 asserts an

acknowledge on SDA.

4. The master sends the Command Register Address 0x00.

The slave asserts an acknowledge on SDA.

5. The master sends the first Data Byte 0xE0 to the

Command Register, which selects the VIN1, VIN2 and VIN3

channels.

The slave asserts an acknowledge on SDA.

6. The master sends the second Data Byte 0x20 to the

Command Register. The slave asserts an acknowledge on

SDA.

7. The master sends the result register address (0x01). The

slave asserts an acknowledge on SDA.

8. The master sends the 7-bit slave address followed by the

write bit (high).

9. The slave (AD7291) asserts an acknowledge on SDA.

10. The master receives a data byte, which contains the

channel address bits, and the four MSBs of the converted

result for Channel VIN1. The master then asserts an

acknowledge on SDA.

11. The master receives the second data byte, which contains

the eight LSBs of the converted result for Channel VIN1.

The master then asserts on acknowledge on SDA.

12. Point 10 and Point 11 repeat for Channel VIN2 and

Channel VIN3.

13. Once the master has received the results from all the

selected channels, the slave again converts and outputs

the result for the first channel in the selected sequence.

Point 10 to Point 12 are repeated.

14. Master asserts a no acknowledge on SDA and a stop

condition on SDA to end the conversion and exit

command mode.

To change the conversion sequence, rewrite a new sequence to

the command mode. If a new write to the Command Register is

performed while an existing conversion sequence is underway,

the existing conversion sequence is terminated and the next

conversion performed is the first selected channel from the new

sequence. The maximum throughput that can be achieved using

this mode with a 400 kHz I2C clock is (400 kHz/18) =

22.2 kSPS.

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