ADE7858 datasheet(34/76 Pages) AD

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ADE7858

Preliminary Technical Data

Rev. PrA| Page 34 of 76

0.1

-25

-20

-15

-10

-5

Figure 40. Frequency Response of the LPF Used

to Filter Instantaneous Power in Each Phase

The ADE7858 stores the instantaneous total phase active

powers into AWATT[23:0], BWATT[23:0] and CWATT[23:0]

registers. Their expression is:



cos















PMAX

xWATT





(19)

where: x=A, B, C,

UFS, IFS are the rms values of the phase voltage and current when

the ADC inputs are at full scale.

PMAX=33,516,139 is the instantaneous power computed when

the ADC inputs are at full scale and in phase.

The xWATT[23:0], x=A, B, C waveform registers may be

accessed using various serial ports. Refer to Waveform

Sampling Mode chapter for more details.

Active Power Gain Calibration

Note that the average active power result from the LPF2 output

in each phase can be scaled by ±100% by writing to the phase’s

watt gain 24-bit register (AWGAIN[23:0], BWGAIN[23:0],

CWGAIN[23:0]). xWGAIN, x=A,B,C registers are placed in

each phase of the total active power data path. The watt gain

registers are twos complement, signed registers and have a

resolution of 2-23/LSB. Equation (20) describes mathematically

the function of the watt gain registers.



















gister

Gain

Watt

Output

LPF

Data

Power

Average

(20)

The output is scaled by −50% by writing 0xC00000 to the watt

gain registers and increased by +50% by writing 0x400000 to

them. These registers can be used to calibrate the active power

(or energy) calculation in the ADE7858 for each phase.

As previously stated, the serial ports of the ADE7858 work on

32, 16 or 8-bit words and the DSP works on 28 bits. Similar to

registers presented in Figure 15, AWGAIN, BWGAIN,

CWGAIN 24-bit signed registers are accessed as 32-bit registers

with 4 most significant bits padded with 0s and sign extended

to 28 bits.

Active Power Offset Calibration

The ADE7858 also incorporates a watt offset 24-bit register on

each phase and on each active power. AWATTOS[23:0],

BWATTOS[23:0], and CWATTOS[23:0] registers compensate

the offsets in the total active power calculations. These are

signed twos complement, 24-bit registers that are used to

remove offsets in the active power calculations. An offset can

exist in the power calculation due to crosstalk between channels

on the PCB or in the chip itself. The offset calibration allows the

contents of the active power register to be maintained at 0 when

no power is being consumed. One LSB in the active power

offset register is equivalent to 1 LSB in the active power

multiplier output. With full scale current and voltage inputs, the

LPF2 output is PMAX=33,516,139. At -80dB down from the

full scale (active power scaled down 104 times), one LSB of the

active power offset register represents 0.032% of PMAX.

As previously stated, the serial ports of the ADE7858 work on

32, 16 or 8-bit words and the DSP works on 28 bits. Similar to

registers presented in Figure 15, AWATTOS, BWATTOS,

CWATTOS 24-bit signed registers are accessed as 32-bit

registers with 4 most significant bits padded with 0s and sign

extended to 28 bits.

Sign of Active Power Calculation

Note that the average active power is a signed calculation. If the

phase difference between the current and voltage waveform is

more than 90°, the average power becomes negative. Negative

power indicates that energy is being injected back on the grid.

The ADE7858 has a sign detection circuitry for total active

power calculations. As will be seen in the Active Energy

Calculation section, the active energy accumulation is

performed in two stages. Every time a sign change is detected in

the energy accumulation at the end of the first stage, that is after

the energy accumulated into the internal accumulator reaches

WTHR[47:0] threshold, a dedicated interrupt is triggered. The

sign of each phase active power may be read in PHSIGN[15:0]

Bits 8, 7, 6 (REVAPC, REVAPB and respectively REVAPA) in

STATUS0[31:0] are set when a sign change occurs in the

corresponding phase total active power.

Bits 2, 1, 0 (CWSIGN, BWSIGN and respectively AWSIGN) in

PHSIGN[15:0] register are set simultaneously with REVAPC,

REVAPB and REVAPA bits. They indicate the sign of the power.

When they are 0, the corresponding power is positive. When

they are 1, the corresponding power is negative.

Bit REVAPx of STATUS0[31:0] and bit xWSIGN in

PHSIGN[15:0] refer to the total active power of phase x, x=A,B

or C.

Interrupts attached to the bits 8, 7, 6 (REVAPC, REVAPB and

respectively REVAPA) in STATUS0[31:0] register may be

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