ADE7858 datasheet(30/76 Pages) AD

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ADE7858

Preliminary Technical Data

Rev. PrA| Page 30 of 76

VAP

PGA3

ADC

IAP

IAN

PGA1

ADC

Phase

Calibration

APHCAL=57



Phase compensation achieved

delaying IA by 56us

50Hz

Figure 35. Phase Calibration on Voltage Channels

REFERENCE CIRCUIT

The nominal reference voltage at the REFIN/OUT pin is 1.2±1% V.

This is the reference voltage used for the ADCs in the

ADE7858. The REFIN/OUT pin can be overdriven by an external

source, for example, an external 1.2 V reference. The voltage of

the ADE7858 reference drifts slightly with temperature; see the

Specifications section for the temperature coefficient

specification (in ppm/°C). The value of the temperature drift varies

from part to part. Because the reference is used for all ADCs,

any x% drift in the reference results in a 2x% deviation of the

meter accuracy. The reference drift resulting from temperature

changes is usually very small and typically much smaller than

the drift of other components on a meter. Alternatively, the meter

can be calibrated at multiple temperatures.

If bit 0 (EXTREFEN) in CONFIG2[7:0] register is cleared to 0 (the

default value), the ADE7858 uses the internal voltage reference. If

the bit is set to 1, then the external voltage reference is used.

CONFIG2 register should be set during PSM0 mode. Its value is

maintained during the PSM3 power mode.

DIGITAL SIGNAL PROCESSOR

The ADE7858 contains a fixed function Digital Signal

Processor (DSP) that computes all powers and rms values. It

contains various memories: program memory ROM, program

memory RAM, data memory RAM.

The program used for the power and rms computations is

stored in the program memory ROM and the processor

executes it every 8KHz. The end of the computations is signaled

by setting bit 17 (DREADY) to 1 in STATUS0[31:0] register. An

interrupt attached to this flag may be enabled by setting bit 17

(DREADY) in MASK0[31:0] register. If enabled, the

IRQ pin

is set low and status bit DREADY is set to 1 at the end of the

computations. The status bit is cleared and

IRQ pin is set back

high by writing STATUS0[31:0] register with bit 17 (DREADY)

set to 1.

The registers used by the DSP are located in the data memory

RAM, at addresses between 0x4000 and 0x43FF. The width of

this memory is 28 bits.

As seen in Power Up Procedure section, at power up or after a

hardware or software reset, the DSP is in idle mode. No

instruction is being executed. All the registers located in the

data memory RAM are initialized at 0, their default values. The

0x0000. The RUN[15:0] register needs to be written with

0x0001 in order for the DSP to start code execution. It is

recommended to first initialize all ADE7858 registers located

into the data memory RAM with their desired values and then

write RUN[15:0] register with 0x0001. In this way, the DSP

starts the computations from a desired configuration.

There is no obvious reason to stop the DSP if the ADE7858 is

maintained in PSM0 normal mode. All ADE7858 registers

including ones located in the data memory RAM can be

modified without stopping the DSP. However, to stop the DSP,

0x0000 has to be written into the register RUN[15:0]. To start

the DSP again, one of the following procedures must be

followed:

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