ADE7858 datasheet(40/76 Pages) AD

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ADE7858

Preliminary Technical Data

Rev. PrA| Page 40 of 76

0x3FFF FFFF to 0x4000 0000. If the reactive power is negative,

the var-hr register becomes half full when it decrements from

0xC000 0000 to 0xBFFF FFFF.

Setting bit 2 in MASK0[31:0] register enables the REHF

interrupt. If enabled, the

IRQ pin is set low and the status bit

is set to 1 whenever one of the energy registers xVARHR (for

REHF interrupt), x=A, B, C becomes half full. The status bit is

cleared and

IRQ pin is set back high by writing STATUS0

Setting bit 6 (RSTREAD) of LCYMODE[7:0] register enables a

read-with-reset for all var-hr accumulation registers, that is, the

registers are reset to 0 after a read operation.

HPFDIS[23:0]

HPF

AVGAIN

Digital

Integrator



AIGAIN

APHCAL

AVAROS



ACCUMULATOR

VARTHR[47:0]



32 bit register

AVARHR[31:0]

Digital Signal Processor

Total

Reactive

Power

Algorithm

REVRPA bit in

STATUS0[31:0]

AVARGAIN

HPFDIS[23:0]

Figure 45. ADE7858 Total Reactive Energy Accumulation

Integration Time Under Steady Load

The discrete time sample period (T) for the accumulation

signals on the analog inputs, a 90° phase difference between the

voltage and the current signal (the largest possible reactive

power), the average word value representing the reactive power is

PMAX=33,516,139=0x1FF6A6B. If the VARTHR[47:0]

threshold is set at PMAX level, this means the DSP generates a

pulse that is added at var-hr registers every 125 μs.

The maximum value that can be stored in the var-hr

accumulation register before it overflows is 231 − 1 or

0x7FFFFFFF. The integration time is calculated as

min

125

FFFF

FFF

Time









(35)

Energy Accumulation Modes

The reactive power accumulated in each var-hr accumulation

32-bit register (AVARHR, BVARHR, CVARHR) depends on the

configuration of bits 5, 4 (CONSEL) in the ACCPMODE[7:0]

configurations are described in Table 15. Note that IA’/IB’/IC’

are the phase-shifted current waveforms.

Table 15. Inputs to VAR-Hr Accumulation Registers

CONSEL[1,0]

AVARHR,

AFVARHR

BVARHR,

BFVARHR

CVARHR,

CFVARHR

VA × IA’

VB × IB’

VC × IC’

VA × IA’

VC × IC’

VA x IA’

VB × IB’

VB=-VA-VC

VC x IC’

VA x IA’

VB × IB’

VB=-VA

VC × IC’

Bits 3, 2 (VARACC[1:0]) in ACCMODE[7:0] register determine

how CF frequency output may be generated function of the

total active powers. While the var-hr accumulation registers

accumulate the reactive power in a signed format, the frequency

output may be generated in signed mode or in sign adjusted

mode, function of VARACC[1:0]. See Energy to Frequency

Conversion chapter for details.

Line Cycle Reactive Energy Accumulation Mode

As mentioned in Line Cycle Active Energy Accumulation Mode

section, in line cycle energy accumulation mode, the energy

accumulation can be synchronized to the voltage channel zero

crossings so that reactive energy can be accumulated over an

integral number of half line cycles. In this mode, the ADE7858

transfers the reactive energy accumulated in the 32-bit internal

accumulation registers into xVARHR[31:0], x=A,B,C registers

after an integral number of line cycles, as shown in Figure 46.

The number of half line cycles is specified in the

LINECYC[15:0] register.

The line cycle reactive energy accumulation mode is activated

by setting bit 1 (LVAR) in the LCYCMODE[7:0] register. The

total reactive energy accumulated over an integer number of

ahlf line cycles or zero crossings is accumulated in the var-hr

accumulation registers after the LINECYC number of zero

crossings is detected. When using the line cycle accumulation

mode, bit 6 (RSTREAD) of the LCYCMODE[7:0] register

should be set to Logic 0 because the read with reset of var-hr

registers is not available in this mode.

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